I have a question about inherited connections and ihdl. Short version is ihdl adds a "!" to the terminal db object name in the generated schematic and I didn't expect the "!" there.
According to the manual, I should be able to add some stuff to a verilog netlist which will cause the imported schematic to have a net expression on one of the terminals. For example:
module mymodule(......, MYVDD)
(* netExpr = "MYVDD(MYVDD)" *) input MYVDD;
.....
endmodule
After I run ihdl, what I end up with in the schematic is
terminal name = "MYVDD!" (note the ! which I did not expect)
pin name = "P__69" (not unusual for a schematic pin db object)
default net = "MYVDD!" (here the ! is expected and required)
property name for the terminal net expression = "MYVDD" (also expected)
If I check the result of dbGetTermNetExpr(term) it is "[@MYVDD:%:MYVDD!]" as expected.
What I'm wondering about is the presence of "!" in the terminal name. When I create a schematic by hand in virtuoso with an attached net expression, I don't get the "!" in the terminal name. Is there a way to tell ihnl to not add the "!" to the terminal name?
Should I worry about this? There can be so many tools that may be used at some point in a design cycle (Virtuoso Schematic, Layout-XL, Assura, PVS, auCdl, spectre, UNL, AMS, UNL, Innovus, ultrasim, VPS, Voltus-Fi, dspf, av_extracted, .....) that a name I wasn't expecting or that is different from before always makes me wonder which tool will get unhappy with me in a confusing and hard to find way.