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Title Block strings
Hello everyoneI have some questions regarding title blocks in Cadence Virtuoso. Unfortunately my research has not yielded any results so far.I am currently making my own Title Block / sheet border with...
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why in ADE XL monte carlo simulation, the default number of runs is set as 200 ?
Can anyone explain how the number of runs influence the results?
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VPWLF source in Cadence Virtuoso
Hi,I want to give a voltage ramp signal for a circuit. I am using Vpwlf instant available in analogLib.This works fine if i have same file for all the corners.But I want to run the simulation at...
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Transient PLL spur simulation setup
Hi, Officers, I have a question on how to accurate estimate the spur at PLL output by using transient simulation with DFT function in SpectreRF. For example, if the spur is located at 100 kHz offset...
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Tests/Expressions/Plotting
Dear Cadence Experts:I have two questions regarding Tests/Expressions/Plotting in ADE-XL.I am using ADE-XL from virtuoso version IC6.1.7-64b.500.14. In my test bench I have a number of tests each...
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Stability Analysis (stb) OTA for active RC integrators
Hello,I am designing a CT sigma-delta modulator with active-RC integrators. I have designed my OTAs and performed manual analysis and compensation of the CMFB loop (I could perform correctly the stb...
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Convergence problem
Hi,Im trying to simulate a circuit but its showing me convergence error and bad pivot, so I checked yes for the dc_pivot _check (simulation-> options-> analog) but the error still persist.Also,...
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transient simulation accuracy
Hi, I am using an ideal delay cell in analoglib. With defined 1 ps delay, the cell is sometimes behaving abnormally with changed slopes. The smaller time strobe and max time step may solve this...
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ADE Distributed Job Name History
Running Virtuoso version ICADV 12.3-64b.500.19Submitting jobs in ADE with the Distributed Processing option Job Submit form.The first field is 'Job Name', it automatically started at job001 and...
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Check if a library exists in cds.lib or included cds.lib files from terminal
Hi,Is there any cadence utility to check if a library is defined in cds.lib or any included files? I wish to use the utility from terminal.Thanks,Bala
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Assura Default License
Hello:I run Assura LVS and it returns a license error: Run 'lic_error LMF-02012' for more information.Failed to obtain license for "Assura_LVS". Checking out license for Phys_Ver_Sys_LVS_XLLVS...
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Max point number in local optimization
Hi,When I do a local optimization in virtuoso, it simulates only 11 points but I configured much more options in my variables. I would like to increase this number but I didn't find any option. Could...
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custom cap cell from tsmc 0.18um process
hello exports,very dumb question, how should I customize a new cap cell so that I can build my circuits upon? I know I'll need cell symbol, layout, and DRC checked. how should the parasitics be...
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Extracting Noise Plots of Isolated Devices using Single Simulation
Hello,I created a small test bench with two transistors. The two transistors are completely isolated from each other. In the noise simulation setup, I am forced to define an output node. If I define...
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Plot transient OP vs. Time
Hi,I want to plot the transient operating point of a device versus time (e.g device Msrowin, operating point for ids).One way to achieve this is to create a file "tran_op.scs" and include it with the...
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ADE Assembler sweep config views problem
Hi,I have a simulation setup in ADE Assembler including a sweep of configs of a sub-module (like expained here: community.cadence.com/.../sweeping-multiple-config-views).Let's say I have a config_a and...
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dump for particular hierarchy.
Hi ,we have top file , top file having so many hierarchies after running simulation will get the dump for total top file.what i need is , out of so many hierarchies i need the dump for particular...
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Gravity Snapping in IC 6.1.7
Hello,How can I enable gravity snapping to center of objects/layers in Cadence Virtuoso Layout? This was previously available as a check box in the Layout Editor Options.Thanks.
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Extract schematic from layout or verilog code
Hello,I am a full-custom analog designer but for my project I had to design a semi-custom part. I want to do an overall LVS but I cannot make netlist. I read a lot of article and web sites to do it but...
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Accessing ADE XL global variables from within systemverilog block
Using ADE XL. I've got a Spectre DUT and am using systemverilog to generate my testbench stimuli. I need to access global variables from within the SV testbench so that I can uniquify result...
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