Extract schematic from layout or verilog code

Hello,

I am a full-custom analog designer but for my project I had to design a semi-custom part. I want to do an overall LVS but I cannot make netlist. I read a lot of article and web sites to do it but it is not clear at all. My technology is UMC180nm. The standard cell are provided by Faraday and they only provides layout (not only a symbol). So I cannot make any schematics from verilog. I also tried to make a netlist from layout to make a schematic afterwards but this also did not work. Can you please help me on this issue. My deadline is very close and I do not know how to do this.

Thank you so much in advance,

Best regards,

Reza