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[URI] RelXpert support for HISIM_HV model cards.
Hello All,I am implementating an aging model using the URI for a transistor techonology using a HISIM_HV model card. The implementation works fine when I run the simulation using the Spectre Native...
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Image Rejection of IQ mixer
What is the easiest way to simulate image rejection of an I/Q downconversion mixer - if possible with pss/pac?Suppose the mixer is a black box with a PORT at the LO input (which generates 0 and 90...
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Error detected in psf library while writing to file `tran.tran'.
Hi,I am using virtuoso to simulate my 30k gates design and in the process i am saving all the signals along with power signals.After 2.5ms (2.27 %) of the simulation, i am getting a fatal error "...
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Changing x-value of a signal and/or handle signals with multiple outputs
Hello,My question from https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/38589/image-rejection-of-iq-mixer is still up :( So far I found the following hack: PSS+PAC, relative...
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How can you move/stretch schematic wires WITHOUT Virtuoso rerouting...
I did try searching for this answer, but got lost in the zillions of search results so I thought I'd try here...I have a schematic that I've carefully and neatly laid out. If I edit it to do things...
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File Type Clarity - Using Built-in Capture Symbol Models to Create...
What I'm trying to do... I need to simulate two NMOS transistors each with custom parameters. I would like to have my own Library in which I can build individual non-associated (meaning: if I...
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IC617 import GDS file from TSMC.
Hi, Can I ask a favor?I am trying to import an io pad lib from TSMC into Cadence IC 617. This is how I tried to do it.I firstly create a library , name it io_pad and attach it to my TSMC PDK library...
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Cadence simulation setup－core usage-
Hi teamI have posted this question on other EE forums and received conflicted answers. But I think no where can give me a better answer then here. So here we goNow I am using CADENCE IC 617 and...
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Innovus CTS for a range of clock
Lets assume, I have a clock source whose frequency can very within a range (like within 6MHz to 9MHz range).I have a verilog circuit module where I would like to use this clock.How can I configure...
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QRC Lvs Extracted View
I am using QRC with LVS Extracted View output in order to generate the circuit netlist from the layout.The netlist (created with ADE-L) is the reported below. However I would like to add a custom extra...
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PAC + PSS for a single-inductor multiple-output (SIMO) converter with verilogA
I would like to run PAC + PSS for a single-inductor multiple-output (SIMO) converter to plot small signal transfer function from duty cycle to each ouput of the converter. However, some blocks of the...
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How to do "multiplication" in freq. domain with provided noise data file?
Hi all,Recently I've been doing some noise evaluation issue, the simplified testing environment is as below:The thing I want to do is to multiply the noise profile defined in both "AVDD" and...
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Performance of BSIM-CMG 110.0.0 FinFET SPICE model in spectre simulator
Hello,recently I got interested in the BSIM-CMG FinFET SPICE model.Looking at the Verilog-A reference code I wonder what performancecan be achieved on current multi-core/multi-threading Xeons...
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flattening a cell in a library
Hello!I want to flatten a certain cell, say cell_A, inside all of the cells in a library that contain this cell_A.How do I do it using a skill code?TIA
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how to enforce identical MC mismatch variation on sub circuit used for...
good afternoon,For a high dynamic range CT SD ADC we need a few calibrations prior to running MC process & mismatch verification. We were wondering about possibility to run these (analog)...
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Liberate for .lib generation of D flip flop
Hi,I'm trying to characterize a D flip flop using Liberate_AMS. Here for the stimulus I'm creating a delay table (rather than using a test bench and using the define_deck command)....I'm getting the...
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Filter Layout pins from LVS
Hi,The LVS extract some devices with 3 pins, while in the corresponding schematic device has 2 pins.I need to extract the third pin in the layout in order to include a customized model.Is it possible...
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Will different save options cause different Spectre simulation time?
Hi,I’m using Spectre in ADE L to run simulation. When setting ‘selected’ in ‘Select signals to output(save)’, it elapsed about 135 seconds. Setting ‘allpub’, it elapsed about 172 seconds. Of course,...
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Device parameters not netlisting in LVS
I am trying to netlist device parameters in LVS. I am using the standard measureParameter and nameParameter command. But the parameters are not getting netlisted. This is usually a simple operation and...
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Suggestions for practical ADE Assembler test setup for corner-specific...
Hi,Our design teams use corner-based extraction cell libraries. These extractions are saved as various views in each cell. We are interested in convenient ways to specify distinct views per corner...
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