Control flow when a return from an expression is nil
When my cross command fails to cross the threshold, it gives eval err in the result.I want the test to give default value, i.e., uncalibrated value, so the next test have something to compare...
View ArticleExporting device component values and operating conditions into a table in...
Hello All,Is there a way to Export the design's device (mainly transistors) component values (W,L , M ...) and operating conditions (vds , vgs ..) into a tablular format either csv , excel ... ?I am...
View Articleleaf cell issue with using diffstbprobe
I have a fully differential amplifier design and wish to look at gain/phase. I've instantiated diffstbprobe between outputs and inputs, and on the prompts, selected I3/IN1 and I3/IN2 as the "probe...
View ArticleIs it normal for DeCap to get 0 value leakage power when running liberate?
Our soi DeCap with 5 terminals (VBGP/VBGN is the 5th terminal) share the same power template with standard cells, however, the leakage for DeCap is 0 value while standard cells get leakage power like...
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Run Options of ADE Assembler in Cadence Virtuoso
HelloI would like to ask you about the Run Options in ADE Assembler as seen in the image belowThough I read the help but couldn't figure out the purpose of this option,Actually, I am interested in any...
View ArticleAccessing power results from transient analysis in spectremdl
Hello.I want to be able to access power/energy results obtained form a transient analysis and be able to pass them to an mvarsearch.How can I do this? I don't seem to be able to access the power using...
View ArticleAny efficient way to do calibration using calcVal and MonteCarlo for tripple...
I basically want to execute a calibrated simulation.The inner loop sweeps the design variable.The second loop sweeps the code.The third loop, i.e., the outer most loop, runs the MC.I can do this by...
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Cannot select signals to be saved in ADE Explorer/Assembler; net listing is...
Hi,I am struggling with a very basic bug(?): ADE Explorer/Assembler just won't let me properly save current signals of a bus of an instance:I can't select "Save" for a signal, no matter how often I...
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Matlab Error When Starting from Assembler
I am getting a Matlab error when I try to start Matlab using the Assembler results toolbar button. The error is an "Invalid use of operator".I think the problem is, the run command ADE is trying to...
View Articlequestion ： standard cell symbol import to virtuoso
I want to import TSMC 65nm standard cell library into virtuoso.The. SPI file was successfully imported into schematic, but I used xxpwr.v importing symbol, some errors occurredThe following is the...
View Article$analog_node_alias() usage with vector nets
Hello,I have a top testbench containing design under simulation (DUT - schematic) and next to it I would like to have a checker built with verilogA. My intent is to use $analog_node_alias() or...
View ArticleMaestro - Elapsed time to results
Hi.Is there a way to add elapsed time (time take to corner to run, I see it in log file) to results for test ?Thank you in advance.
View ArticlePolysilicon in 180nm TSMC
Hi all, I'm going crazy in understanding what is poly layer in 180nm TSMC. From my knowlodge i know is n+ polysilicon. From the DRC error looks like is p+ because the error call the poly as P GATE. In...
View Articleillegal weak connection warning issue
Hello, In the layout of my circuit, and by using the "Check against Source", I receieve connectivity note in CAS telling me about illegal weak connection of some of my signal paths,As for example, I...
View ArticleVirtuoso License Issue: status code -5.
Hello Everyone,I am facing some issues when working with Virtuoso Suite.Sometimes the program freezes for some seconds and the message below is shown in the main window:*WARNING* (icLic-203) Failed to...
View ArticleWay to automatically print the noise summary after noise analysis
Hi All,I am performing noise analysis on a circuit using IC618 and as of now printing the total integrated noise summary after every iteration using the Results -> Print option.Is there a way to...
View ArticleTestbench for THD and IIP3 simulations
Dear all,I plan to simulate THD and extract IIP3 of a single transistor by using PSS and PSS+PAC analysis in cadence. I have used the testbench attached below to run simulations. Two bias tees are...
View ArticleIC 6.1.7 on RHEL8
Hello all,I was wondering if someone could tell me if Cadence IC 6.1.7 works on a RHEL 8 machine. I have it working on CentOS7, but when i try to launch virtuoso from RHEL8, I get the following...
View ArticleRunning more tests in an already finished interactive window
I have a test that's already finished running. But now I want to simulate it again *in the same interactive window" with a different value for the design variable. The reason I want it to be in the...
View Article3DB bandwidth expression
Hi All, I am trying to evaluate a function using the expression editor but am getting an error. This is for bandwidth of differential output divided by the differential input as shown below....
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