Clik here to view.
Can I start a simulation in the mid night?
Hi Senior engineers,Is it possible to start sim at midnight using the GUI?GUI = ADE-L, assembler, explore...Simulation = DC, tran, AC...best regards,Ichiro
View ArticleClik here to view.
Partially auto via
Can I float the existing metal and draw it automatically when I run Autovia???I am sorry for my poor English....
View ArticleClik here to view.
Not able add pins to symbol; restricted by string length
Hi,I have been trying to create a symbol with considerably large number of pins. I am adding required pins in "pin specifications" of "symbol Generation Options" dialogue box. But after a certain...
View ArticleClik here to view.
Error When Running AMS Simulations with Both VHDL and Verilog in Digital...
Hello,I am attempting to run an AMS simulation including a digital block consisting of both VHDL and Verilog in the digital heriarchy.The question is in two parts. The first part relates to how I'm...
View ArticleClik here to view.
Cadence Virtuoso Jop Policy Setup
Hello,I am using Cadence Virtuoso IC6.1.8-64 bit.550.6,I would like to ask about the Jop Policy setup, what does the option "Max Jops" refers to, if I increase this number will I have faster...
View ArticleClik here to view.
Control precision/significant decimals in ADEXL results
HiCan someone please suggest a method to control(increase/decrease) the number of displayed digits of the fractional part in ADEXL results summary table?I do see the following in the Menu...
View ArticleClik here to view.
Import data (.csv file) to Cadence
Hello,How can I import data (.csv file) file into the cadence?I am using Virtuoso spectre.I am using Python to generate the .csv file from MNIST dataset.Thank you.Mai
View ArticleClik here to view.
ViVa Bookmarks and its usage
Hello everybody,I recently discovered through another post here on the forum the VIVA function (see below) to include bookmarks on the charts. This one below create a red area from 2.11 GHz up to 2.66...
View ArticleClik here to view.
Verilog-A: How to trigger event, if input parameter changes in DC sweep
In my analog testbench, I have a Verilog-A block which is using an integer parameter. This parameter is set in the testbench via a variable in my Maestro view. Now I want to sweep over this variable,...
View ArticleClik here to view.
How can I reverse the color of the black background and the white axis value?
This is my simulation result.How can I reverse the color of the black background and the white axis value and axis?I want to reverse the color of the black background and the white axis value and axis,...
View ArticleClik here to view.
Cadence Liberate CCS Power Characterization Accuracy
Hi, I am comparing the CCS characterization accuracy of cells in a shift register with its spice simulation. The power characterization settings used in Liberate looks like...
View ArticleClik here to view.
DC sweep with a static cap voltage
I am designing a RF power detection circuit with an auto zero function. When the circuit is enabled it stores amplifier input offsets on capacitors which hold that voltage to cancel the offsets during...
View ArticleClik here to view.
Backup and reload results in Assembler
I'm using ADE Assembler (IC6.1.8) to run some heavy Monte Carlo sims, but my simulation drive is running out of space. Half way through, I get a low disk space warning, simulation comes to a halt and...
View ArticleClik here to view.
Is there leakage current in Analoglib's cap?
I wonder whether leakage current occurs in analoglib's cap.Please tell me about this.Thank youyysunj
View ArticleClik here to view.
Why Kirchhoff's Current Law is not satisfied at my circuit?
I designed a circuit and applied voltages (DC voltage or Pulse) to each node. (Please refer to the uploaded file.)And, I performed transient simulation under given situation.However, At node N of my...
View ArticleClik here to view.
order of output evaluation in maestro results pane
can I set the order in which maestro outputs are evaluated (executed) after simulation finish?Currently outputs seem to be evaluated in parallel (simultaneously) as simulation ends, while I need them...
View ArticleClik here to view.
Question about exporting simulation results to csv format, with ocean script
Hello,I have a question about ocean script.As I mentioned on title, I'm trying to do ac simulation and export simulation results to csv file.In ADLE gui, I could do it by clicking some buttons, like...
View ArticleClik here to view.
FATAL: The following branches form a loop of rigid branches (shorts) when...
Hello,I am getting fatal errors at the time of the simulation. Using Verilog-A view only.Please help to debug these issues.====Errors:====Notice from spectre during initial setup. Ignorevaref=yes is...
View ArticleClik here to view.
Swap Activity Warning: Excessive swap activity
Hello,While I was doing post-layout simulations, I'm encountering with a problem of excessive swap activity (Attached the image for reference) and machine got stuck afterwards. I have tried with...
View ArticleClik here to view.
Sine wave amplitude-modulated by a ramp for transient simulation
Hi,how can I create a sine wave waveform whose amplitude is modulated by a ramp, in the time domain? Using analogLib components..I mean something like:at t=0: Vampl=Vampl_minat t=t_sim_final:...
View Article