Hello,
I am attempting to run an AMS simulation including a digital block consisting of both VHDL and Verilog in the digital heriarchy.
The question is in two parts. The first part relates to how I'm setting up the simulation as maybe that's where I'm going
wrong. The second part is the error I'm getting during compilation.
First Part: I have a digital behavioral block with multiple levels of hierarchy. I read in the top level block using Verilog-In to
create a symbol view. I then instantiate this block in a test bench schematic and use the Hierarchy Editor to point to the
symbol view. In the Simulator->AMS Options form I include all the Verilog files and VHDL files in the Netlister tab for the whole
digital hierarchy including the top level. Is this a valid way of running AMS using a digital block with hierarchy or is there
something fundamentally wrong with this approach?
Second Part: I set the simulator to 'ams' and the 'Netlist and Run Options' to use the OSS-based netlister with irun' The design
netlists with no problems but the compiler fails when it tries to compile the VHDL blocks with 'expecting the keywork 'module' and
numerous errors of 'illegal base specification'. My understanding is that irun should be able to run with both VHDL and Verilog at the
same time but it seems there is a problem with the VHDL blocks.
Thank you for any help,
Anand