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Monte Carlo - RAM usage issue, run each point consecutively?
Hi,I have the same question as this 10 year old post:community.cadence.com/.../is-there-a-way-to-prevent-monte-carlo-runs-from-accumulating-ever-more-ram-space-memoryI try to run Monte-Carlo on a large...
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Simulating a DAC in Cadence
hiI am trying to simulate a 8-bit DAC in Cadence I want to input all digitial input combinations from 00000000 to 11111111 (0 to 256) incrementing by 1 each time and also I can also hold it on a...
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deepprobe gives error when probing: --- WARNING (SPECTRE-8281): `p0' is not a...
I am instaniating an analogLib/deepprobe instance at the top level of my schematic to allow probing inside an extracted netlist.This instance shows up like this in the netlist:IPRB2...
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Reconciling phase-noise obtained using pss+pnoise analysis with that obtained...
Hi Andrew, The phase-noise simulation results obtained using pss+pnoise analysis is found to be around 10dB lower at various offsets than that obtained from transient noise analysis. The nominal...
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How can I change several tests on Assembler simultaneously?
Hello,If I have an Assembler maestro setup with several sub-tests and I want to make the same change to all of the sub-tests how would I do that?E.g. say I want to change the model files used, or...
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Developing LPE with a custom ICT file
Hi all,For a research project, I need to develop a Layout Parasitic Extraction tool for a novel technology as an addition to a developed PDK. To do this through Quantus I had to write my own ICT file....
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*ERROR* (AMS-1245): AMS UNL netlisting" in AMS simulation
Dear All,I am running a AMS simulation for a testbench. When add a particular cell form a library to it, I see the following error.*ERROR* (AMS-1245): AMS UNL netlisting *ERROR* (AMS-1245): AMS UNL...
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Spectre/APS: how to save only subckt and some level below it
I think this might be an old topic, but I just could not locate some of them. My question1> How to save all voltage signals from a certain block and its sub levels? For example, we have a fullchip...
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Plotting a Graph in cadence with different axis variables DC-Analysis Design...
I implemented a cascade current mirror circuit as shown blow.And I want to plot the output voltage Vout relative to the changes of input current (0<Iref<800uA) . I use...
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[AWR Microwave Office] Issue related to plot of contours
Dear All,I've quite big problem related to contours in AWR. I can generate LP_Data file of an amplifier from load-pull analysis implemented in AWR. Moreover, I can plote parameters such as PAE, Gain,...
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ERROR EMX in virtuoso
I am trying to simulate an inductor in EMX.I am getting following error:-*Error* hiGetTextWidth: argument #1 should be a string (type template = "t") - text Please help me with this.
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Variable set in corners overrides variable locally defined in test
Cadence_icadvm v18.10.130ADE AssemblerI am running a trimming (calibration) simulation. The trimming must be done at a fixed supply voltage. Thereafter, I want the post-trim test to take the value set...
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Problem in simulating an inverter using BSIMCMG
Dear All,I'm using BSIM CMG model for simulating GAAfet behaviour so I have created (by importing verilogA files) 2 different symbols for ntype and ptype transistors.I managed to plot their...
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Techgen Error: Starting Triangle not defined
HI all,I am trying to generate a qrcTechFile using Techgen and my own ICT file. However, I have run into a problem. My first question is whether I am running Techgen correctly (I have never worked with...
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Virtuoso schematic set net to default to a certain color
HiIs it possible to set a default color for specific nets that are local to a schematic? I have some mildly complicated schematics and they're very repetitive and some signals go everywhere and other...
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Analysis was skipped due to inability to compute operating point.
I am trying to simulate a very simple design using a dc current source and a switch. I keep getting Analysis was skipped due to inability to compute operating point.Could you please help me with...
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Convergence issue with Verilog-A model
I have developed Verilog-A model of a device that I am trying to simulate and every time it gives different value and at most of the occasions it just stops at a certain time of the simulation. I have...
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Mismatch simulation in Monte Carlo
Hi,I am investigating Mismatch in the multipliers. I made a very simple testbench with two transistors having identical VGS voltage, one with 1 multiplier and the other with exact same sizing and 64 as...
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The Principle of Automatic Sweeping
Hi all.I want to know how automatic sweep of dc analysis works. I'm doing now a DC sweep analysis with 192 corner patterns.In this simulation, I need to verify thresholds of a CMOS Inverter in 1 mV...
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Problem in doing pss pnoise simulation to get PFD CP output current noise
I tied an ideal voltage source to the output of my charge pump and selected this voltage source as the port of my pnoise simulation. However, after my pss pnoise simulation is finished, the output...
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