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Can we use $table_model() in verilogAMS
Dear All,I have used $table_model() in VerilogA.But while using it in Verilog or VerilogAMS, I am seeing errors.So, Can we use $table_model() in verilogAMS ?Kind Regards,
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Virtuoso 18.1
Hi,Getting the warning message while trying to use the router in virtuoso18.1,*WARNING* "Command wrongway_pin_escape requires application feature Router only that cannot be licensed".*WARNING* TCL...
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Error in running AMS simulation
I have a simulation with a systemVerilog module and an analog block and trying to simulate them together.1. Using ADE XL2. Have set the simulator to ams3. Set my connect rules4. Made config view with...
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Getting SKill Script From GUI History
How Can I get the Skill script behind my GUI command? For example, from the menu bar clicking on Connectivity -> XL Probe, I want to add a bind key for opening XL Probe. Hence, I need to get the...
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Importing corner setup from CSV with double quotes
I would like to import my "corner setup" into ADE Assembler from a CSV file.One of the variables defined is a file name that needs to be specified with double quotes or Cadence/Spectre will not run.In...
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VCCAP Usage and Documentation
Hi Guys, I have a question about vccap in the analogue lib.I need to simulate a design with a varying capacitor and hence use a vccap is a good choice.However, I don't quite know how to use it and the...
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Converting Schematic Testbench Setup into Command Line Spice File(s)?
Hi,Assuming I have a complete test bench with timing signals, biases, voltage sources, etc connected to different sub blocks. Is there an easy way to convert this "schematic gui" into a spice level...
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How to delete multiple cells in LibManager
Is there a way in the LibManager to select multiple cells and delete them ?Currently I only can delete one cells after the other, which is a pain if you have more than 10 cells to delete.In my case I...
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Verilog-A switch model with thermal noise modeling
Hello,I am trying to write a verilog-A model for an ideal switch that would be compatible with PSS/PNOISE simulations. The goal is to simulate kT/C noise in switched-capacitor circuits, so I have the...
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Make layout more visible in layout L
In schematic, you can change background, color or bold of wires or devices to make circuits easier to read or put it for presentation. Is there a similar feature for layout L?With default coloring like...
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Symbolic (Analytical) Transfer function from Cadence (XF/PZ) for Simulink...
I am trying to extract a symbolic transfer function from a circuit I have so that I can use that transfer function in Simulink. I am designing a multi-stage op amp and wanted to be able to use the...
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Dynamic Variable
Hi, I have a simulation in ADE assembler where I run a transient sim first and use the final condition of the transient sim (Writefinal -->spectre.fc) as an initial condition to pss sim (readic). In...
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maestro - .tcl file - signals not saved when running monte carlo, single run...
Hi,in an AMS maestro testbench, the internal vhdl variables of a digital instance should be evaluated.This is done by a ams_sim.tcl-file, which has probe statements:probe -create -emptyok -database...
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How to change default schematic symbol colors
Excuse me if this has been asked before but I couldn't find anything.We have a pdk from a foundry where all the schematic symbols have the default green color.We would like to change the color of...
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Cadence virtuoso CDB to OA conversion ( ERROR*loadcontext )
hiI transfer new pdk from CDB to OA format using the conversion toolbox. The conversion is completed without problem but when i create a library > attach it to new pdk this error appear in...
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csh C script for automating the ocean simulation
Dear all,I am trying to build a C script that sets the environment, invokes the ocean software and completes the simulation without any interventions required. (basically automating the whole...
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How to use PSS to determine the output dynamic range ?
Dear all,I am simulate a one stage amp, my mentor ask me to use PSS simulation to determine the THD and dynamic range. I use trans to check the output THD before, but don't know how to determine the...
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Batch export of parasitic values in nets
HiI'm using virtuoso 6.1.8 and have QRC extracting my paracitics. I have a pretty complicated cell and I want to see what the net R and C parasitic values are on my bus - is there a way to batch...
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Print Noise Summary after Pnoise Simulation(timedomain)
Hi Everyone,I need to simulate the noise of my circuit by using pnoise analysis, which is shown as below:unsmpldNoise out 0 pnoise start=0.1 stop=10/t_period maxsideband=200 smpldNoise out 0 pnoise...
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scaling layout
Guys, is there any way to scale a design (layout)? For example, let's say I have a design that includes only metal-1 and I want to scale it both in x and y directions, by a factor of 0.9. Any solution...
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