Below's the exact violation I get. How can I fix it?
FATAL (SFE-2218): "/users/Projects/alpha/models/bsim-cmg_110.00/benchmark_test/modelcard_ak_verilog.nmos.lib" 206: It is not permitted to alter the paramerized module for the instance (`Mmain') currently.
Some background:
1. I downloaded the BSIM-CMG Verilog-A model. Then I followed the instructions from Andrew Beckett in this post 1332112 to create a simulatable cell cell. Everything works fine.
2. I made some edits to original BSIM-CMG model file (added additional white_noise to drain current in bsimcmg_body.include). This works fine the first time I simulate.
3. When I make any edits to my schematic (either related to the cell) or edits to my ADE-L testbench (e.g. change the SP simulation frequency range), I get the error listed above.
4. If I re-save the bsimcmg_body.include file, then I'm able to simulate again without issue.
I don't want to have to re-save every time I make a change in ADE-L or the schematic. Please let me know what I'm doing wrong.