Generating spectre netlist using si gives unexpected bus syntax

Hi,

I'm trying to make a netlist with si. I've created my si.env

simLibName = "myLib"
simCellName = "mySch"
simViewName = "config"
simSimulator = "spectre"
simNotIncremental = 't
simReNetlistAll = nil
simViewList = '("veriloga" "ahdl" "spectre" "schematic" "netlist")
simStopList = '("veriloga" "ahdl" "spectre")
simNetlistHier = 't
nlFormatterClass = 'spectreFormatter
nlCreateAmap = 't
simNetlistHier = t

All my bus signals looses their brackets (myBus_1 instead of myBus\<1\>).

Which option do i need to keep the bus format? 

Best regards,

Christian