Generate SDF for custom digital layout

Hi,

I want to know what is the procedure that I have to follow in order to generate an SDF file from a custom digital layout I made using Virtuoso.
I have the Verilog of the standard cells I used (Clock Buffers, Inverters, etc.) and the .lib for each of the cells. I have also generated the netlist of my digital design from my schematic, using Ncverilog.
Which are the next steps I need to follow?

Thank you in advance for your valuable help!

Kind regards,
anm