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How to insert a probe for stb analysis without disturbing LVS?

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Hi,

to avoid problems in LVS you can use lvsIgnore, but this is only good for few elements like a pcapacitor. I would like to permanently have a series vdc=0 in my schematics, but to avoid lvs problems we need e.g. to replace the vdc with a short. I remember it is possible but forgot the details. Best would be having an analogLib element working for both stb analysis and lvs (but I found nothing so far).

Bye Stephan


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