Cadence version:
IUS: 20.09.012
MMSIM: 20.10.354
My test bench is all digital (functional and systemVerilog, no spectre elements).
This test bench checks if a node value (wreal4state) deep in hierarchy is the same value that comes out of an analog mux at the top level.
I want to sample the value deep in hierarchy and then compare it to the value at the top level. However, with the code I am using, the elaborator is putting an IE R2L on the wreal4state net in hierarchy. So, for example, the value at the top level 1.24, but the sampled value in the stimulus is 1.0 because of the IE.
I looked at this article: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009ESqBUAW&pageName=ArticleContent&shareID=1678896866867
This uses a system function $real_net_alias() that is used in v-ams. When I try to use this, I get this error:
xmelab: *F,WRFUNCM (/design/x/x/x/x/x/x/x/x.sv,1035|30): Can not connect real net TB_xxx.IxxxxSTIM.abus0_mon.w_res with nettype 'wreal1driver' and resolution 'CDS_res_wreal1driver' to real net TB_xxxx.IxxxxSTIM.abus0_mon.signal with nettype 'wreal4state' and resolution 'CDS_res_wreal4state'.
Is there a version of $real_net_alias() for systemVerilog cds_rnm_pkg nets? Or is there a better way to probe the node deep in hierarchy such that it does not add an R2L?
