Quantcast
Channel: Cadence Custom IC Design Forum
Viewing all articles
Browse latest Browse all 4954

ERROR in AMS simulation : "expecting a valid compiler directive [16(IEEE)]"

$
0
0

Dear All,

I have a verilog code portion as below:-

But, when I run I get error as :- ncvlog: *E,EXPCPD ... expecting a valid compiler directive [16(IEEE)]. `#if $NUM_STAGES$ > 2.

Could any body please tell how to fix this issue.

`#if $NUM_STAGES$ > 2
sync_mod i_sync_cell(
.Q(z_o),
.CD(~reset_n_i),
.CP(clk_i),
.D(d_i_sg2),
.SE(1'b0),
.SI(d_i_sg2)
);
`#endif


Viewing all articles
Browse latest Browse all 4954