Hello,
I have a testbench for the cell of a multi-stage amplifier. I placed a dummy resistor between the stages, which allows me to disable it later in a config view of the testbench. This way I can access the corresponding nodes with deepprobes and use an sprobe to analyze the interstage matching without altering the actual schematic of the amplifier.
Is it possible to do this without editing the config view each time? I though of something similar to the deeprobe, where I can place a cell in the testbench and specify an instance name (eg. "DUT.AMP.RES1") or a net (eg. "DUT.AMP./netxy") which gets disabled or left open for the simulation. The "mind" in the analoglib is a another cell, which modifies the behaviour of two normal inductors. Maybe the same approach can be used here?
Best regards
Paul