Hi,
I am trying to perform transistor level post layout simulation on a 'P&R'ed digital design. After P&R and timing optimizations, I import the post layout netlist (without physical only cells) to Virtuoso (Cadence IC 6.1.7) along with extracted .dspf file. I have the OA version of the reference standard cell library in Virtuoso in which all cell views have power and well contacts. However the .dspf from Innovus does not have these contacts in "instance" section, so that when the .dspf is annotated to the schematic netlist, spectre simulation stops throwing following error :
ERROR (SFE-45): `Xpipe_in_0__dxin': An instance of `DFQBRM1RA' needs at least 8 terminals (but has only 4).
The schematic Netlist looks like below:
subckt DFQBRM1RA QB CK D RB VDD VSS VBN VBP
M0 (VSS CK N_2_M0_s VBN) n_12_llrvt l=1E-08 w=1E-07 sa=1.6E-07 \
sb=4E-07 nf=1 mis_flag=1 sd=200n as=2.4E-14 ad=3.315E-14 \
ps=6.2E-07 pd=7.6E-07 sca=45.7965 scb=0.032936 scc=0.00744915 m=1 \
mf=1
M1 (N_3_M1_d N_2_M0_s VSS VBN) n_12_llrvt l=1E-08 w=1E-07 sa=4E-07 \
sb=1.6E-07 nf=1 mis_flag=1 sd=200n as=3.315E-14 ad=2.4E-14 \
ps=7.6E-07 pd=6.2E-07 sca=45.7965 scb=0.032936 scc=0.00744915 m=1 \
mf=1
whereas .dspf :
Xpipe_in_0__umc65_dxin pipe_in_0__umc65_dxin:CK pipe_in_0__umc65_dxin:D
+ pipe_in_0__umc65_dxin:QB pipe_in_0__umc65_dxin:RB DFQBRM1RA
Is there a workaround to bypass this in Virtuoso ?
Thanks in advance
Anuradha