Dear sir, I want to use virtuoso in windows. But I didn't find the guided tutorial till now. Also I'm not sure whether cadence virtuoso can be used in winodws.Wish someone could help me! Thank you.
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Can cadence virtuoso bestarted in windows?
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Can cadence virtuoso bestarted in windows?
Dear sir, I want to use virtuoso in windows. But I didn't find the guided tutorial till now. Also I'm not sure whether cadence virtuoso can be used in winodws.Wish someone could help me! Thank you.
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In which file/cellview are the CDF parameters are stored ?
Hi,
I do have a cell with schematic, layout and symbol view.
Both are checked in into our 3rd party revision control system (Cliosoft SOS).
This cell has some CDF parameters I want to change via the CDF editor.
I am wondering which cell-view I have to checkout to be able to change the CDF parameters.
Are the CDF parameters stored in the schematic or symbol view ?
Or in any other file within this cell (e.g. data.dm) ?
I found some entries in "data.dm" ….
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Ophaned .cdslck file with custom view type
Version info: IC6.1.8-64b.500.10.EHF7015
I have created a custom view type but have a problem with orphaned .cdslck files. The custom view type launches my own external application with a GUI interface for manipulating some proprietary files related to a specific schematic. When the APP closes, the cdslck file is left in the database.
I have tried manually removing the .cdslck file on the linux command line but this creates a new problem. After the manual deletion the cdslck file is no longer created for that library, cell, view (LCV) combination for the Virtuoso session. If I restart Virtuoso, the cdslck file can be recreated for the LCV.
Based upon this, I'm assuming that the Virtuoso session holds a reference to the LCV in memory and marks it as 'locked' and then when the user in the current session attempts to open the same LCV a second time it will skip the portion of the flow that creates the cdslck file.
I found this by implementing code in skill that when on exit, the skill IPC module will 'clean up' the ophaned cdslck file.
My question is related to the proper procedure for opening and closing a custom view type. Are there special commands to tell virtuoso to remove/release the cdslck? We use DesignSync as or data management tool if that has any impact...
Regards,
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Max value of signal in second cycle
I want to find the maximum value of the signal in a particular cycle.
I was using a max function in skill, however, it finds the maximum signal in a complete waveform.
Is there any way or through arguments in a max function, I can trigger its sampling in a particular timeframe?
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How should I modify the sigma value when i used the Cadence Monte Carlo
Hi,
I am using Cadence 6.16 to design the circuit.
I want to know how to modify the mismatch( sigma or std?) of the mosfet when i run the Monte Carlo Simulation. Because i wanna a large mismatch model, as large as possible.
thanks.
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AMS simulation IE (interface elements) for fast edges
Hi,
while doing AMS simulations like SystemVerilog (with EEnet package) in Virtuoso I am stuck with a rise-time limit for my output signals.
The IEs (interface elements) that are automatically put in between analog signals (spectre) and the SystemVerilog domain do have different parameters to adjust the electrical behaviour.
Among these parameters there is "Ts" which defines the sample rate for the interface signal conversion.
The default value is 1ns, but my circuit operates with 800ps pulses and requires a rise-time of <100ps.
I was able to reduce to Ts=500ps and the egdes became faster, but when reducing Ts further the simulation will get stuck and not finish.
I do have the feeling that the "Ts" parameter requires some relation to other time parameters of the IEs or the AMS simulator, but I do now know which ones.
Does anyone know how to setup the IEs and AMS simulation for fast signals with risetimes <100ps ?
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How to create Metal resistor
Hi I write this script but its wrong some where please advice?
///////////////////////////////////
// LAYER DERIVATIONS AND OPERATIONS
///////////////////////////////////
//-----------------------------
// Define Metal resistor
//-----------------------------
//M1RES = ME1 AND PIXELMK
//ME1 = MET1 NOT M1RES
//M6RES = ME6 AND WSYMBOL
//ME6 = MET6 NOT M6RES
//////////////////////////
// Resistor Devices
//////////////////////////
//-------------------------
//-------------------------------------
// Metal resistor
//-------------------------------------
IFDEF XRC_or_CCI
DEVICE R(res M1) M1RES ME1(POS) ME1(NEG)
[
PROPERTY W,L,RES
W = PERIMETER_COINCIDE(ME1RES, ME1) / 2
L = AREA(ME1RES) / W
Rs = 408*W/(W-0.32e-6)
RES = Rs*L/W
]
#ELSE
DEVICE R(res m1) M1RES ME1(POS) WEL(NEG)
[
PROPERTY W,L,R
W = PERIMETER_COINCIDE(ME1RES, ME1) / 2
L = AREA(ME1RES) / W
Rs = 408*W/(W-0.32e-6)
R = Rs*L/W
]
TRACE PROPERTY R(res M1) R R resR_Tol
//TRACE PROPERTY R(res M1) L L 3
//TRACE PROPERTY R(res M1) W W 3
#ENDIF
I believe my if else condition is wrong anyone please advice.
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Changing single transistor instance parameters via SKILL
I have custom transistor compact models that have what amounts to a fail flag. The flag establishes a certain type of behavior for that one transistor when set to one. I would like to be able to set that flag in one single transistor instance in an arbitrarily large hierarchical structure without having it propagate to other instances of identical cells. For example:
I have a top-level schematic view myinverters that contains three inverters wired in series, all of schematic cellview inv1 and they are named I0, I1, and I2. Within inv1 there is a pmosfet and a nmosfet. If I descend into inv1 and modify the fail flag in the pmosfet it will set that flag for all instances of inv1. What I want is a SKILL based approach that will, for example, set only the pmosfet fail flag in I0 and not propagate to instances I1 and I2.
Does a mechanism exist for this type of operation and if so could I get a push in the right direction? A kludgy way would be for me to build a data structure for the hierarchy, find all the fet instances, identify the parent cell, create a copy, modify the one transistor, rebuild the schematic, and simulate from there but I'm hoping for something simpler and more native. I should add that ultimately the goal is, via SKILL, to iterate through all fets in the design (of a known model type), simulating each case, and building a results table of the impact of the fail flag on each.
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ModGen routing problem in Cadence Virtuoso
Hello
I started to work with ModGen (Module Generator), I started the new experiment with simple differential pair transistors as you see from the picture. I followed the Cadence help to create the Modern,
My problem is when I run the routing (after setting the Trunks and Topologies), Cadence will miss the contact of the transistors gates and the sources of the upper array row.
Could you please help me to fix this issue
I am using Cadence Virtuoso IC6.1.8
Many thanks
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Netlist Extraction
Dear all,
Please help me to understand about "Netlist Extraction". I am a new beginner.
Why do we need to perform " Netlist Extraction" in post-layout simulation?
What is the purpose of this?
Thank you advance.
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Gray/Grey schematic for easier viewing of highlighted nets
Back in the days of Cadence 5 I could tap alt-G on the keyboard and my schematic would toggle into gray mode to more easily see and follow highlighted nets through the schematic hierarchy. For the life of me I can't figure out how to get access to that feature in IC 6 (6.1.8). Maybe it was a script the CAD guys had written in the company I worked for at the time. I did search the documentation before posting this but came up blank.
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How to run Cadence Virtuoso using the terminal (VMware Workstation - CentOS)
Hi,
In addition to running Virtuoso using the terminal, how can I open a schematic, a maestro, or a layout view using the terminal?
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Different files formats needed for a complete IC and package design and verification flow
HI All,
Can anyone please let me know what are the different files (and their formats / extensions) required in a PDK to run a complete IC design flow in Virtuoso starting from schematic design to layout drc, pvs, quantus, voltus , voltus-fi, Electromagnetic simulations, package design ?
Or if I can be pointed to any document that explains all the different files formats needed to run the above flow that will be very helpful.
regards
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Re: Environment variables to source from $home/.cadence/dfII
Hi,
Is there an environment that I can set to source file viva.ini from $HOME/.cadence/dfII/viva/viva.ini ? Everytime when I run Virtuoso Visualization and Analysis (VIVA), the software will create a brand new directory and file in the path that I am executing it. I have tried setting CDS_WORKAREA, $CDS_SEARCHDIR, and CDS_PROJECT to $HOME but none of them work.
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Getting/highlighting all input pins of a design in schematic
Hi,
I am working on a huge schematic in virtuoso with lot of pins. I wanted to know if there is any way that I could highlight or get a list of all the input pins only in the design.
Thanks,
Sunny
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Copying layout from cell to other cell issue
Dear Sir / Madam
I am trying to copy a layout from a cell to a different cell, the problem that only MOSFET are copied but non of the rout contacts as shown below. Also please see the error message I receive
here is the layout I want to copy
Here is the result of the copy
and here is the error message
I am using Cadence Virtuoso V IC.1.8
Thank you
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Group as parametric set is not working
I grouped it like this :
And I expect 5 points and I get 3 points :
what am I missing ?
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Finding gain of stage 1 in 2 stage opamp using stb analysis
Hi,
I have a 2 stage opamp in a feedback configuration. I am running stability analysis to find loop gain, gain and phase margin of the opamp. How do I find the gain of stage 1 of the opamp. I see the stability sim only gives the loop gain.
Thanks,
Amogh
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EMX integrated inside Virtuoso
Hi All,
Can you please also let me know which version of Virtuoso has EMX integrated inside it ?
I think EMX was acquired by Cadence a few months back and is integrated now without having to separately launch EMX (please correct me if I am wrong ).
regards
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