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A problem with ports mismatch in LVS

July 10, 2020, 6:09 am
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Hi

I am working by xfab 0.35um technology to design an op-amp but I have encountered with a problem. When I want to run LVS through calibre an error is appeared "different numbers of ports". The ports of schematic are recognized but for layout shows zero ports. I should mention that the LVS is ok when I use assura and doesn't show any errors. For simplification I tried to test this issue only by using one nmos and one port but error still exists. The images of the simulation are attached. I would be thankful if anyone could help me.


Regards

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Can't edit instances

July 10, 2020, 9:15 am
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Hello,

I am not able to edit instances such as transistors. I have never encountered such as thing before. 

It is a 7nm Arizona State University 7nm Finet Predictive PDK

My virtuoso version is:
Version IC6.1.8-64b.500.9
Spectre spectre191

When instantiating a transistor, all I see is the attached image and it is not editable. 

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Defining viva background color changed from IC6.1.7 to 6.1.8?

July 10, 2020, 11:14 am
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Back when I was using IC6.1.7 I had the following in my .cdsinit to get everything on a white background as my default:

envSetVal("viva.rectGraph" "background" 'string "white")
envSetVal("viva.rectGraph" "foreground" 'string "black")

Now that I'm in IC6.1.8 that doesn't appear to work anymore, although the documentation still appears to indicate it would. Every time I run a sim and do a plot I get the usual black background. I can go into the preferences (Edit->MultiGraphProperties) and change it to be white. That preference setting does work (sort of) in that the background color for the current plot changes to white when I click on OK, but the very next time I make a plot it's on a black background again and when I look into the preferences it's still set to be white. Did something change in 6.1.8  and should I be using different commands in my .cdsinit?

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export snp s parameter from multiple conditions in ADE explorer

July 10, 2020, 12:39 pm
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Hi all,

I am run sp simulation over different DC bias condition in ADE explorer. For example, I have 4 bias conditions. I can check plots by sweeping the biases. How can I export 4 snp in one sweeping?

Thank you for looking at it.

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How to handle XL compliance and LVS reduction together

July 10, 2020, 2:02 pm
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Hi,

I am using virtuoso XL and trying to be 100% XL compliant. Now I have created 2 instances in the schematic for a device. The connections are all the same but finer and multiplier differ.

MN3 W=1.818 L=17n nf=2 m=6
MN2 W=3.636 L=17n nf=4 m=1

LVS extracts the devices in layout and finally reduces them to just one 1 instance. Now LVS reports incorrect instance and property mismatch.

(on the schematic side it could not be reduced due to difference in widths)

On the layout side, I have proper devices with equivalent device parameters. 

If I use only one device in schematic something like,

MN3 W=18.18 L=170n nf=2 m=8 , I have a LVS match.

My question is :

Does Only 1-1 mapping of devices qualify as XL compliant? How does it handle device reduction then?

Can I have something that allows me to be XL compliant? I looked up the XL user guide and found many to many binding. 

Is this a possible solution?

Regards

Suryansh 

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Cadence Virtuoso Technology Files and Libraries

July 12, 2020, 8:32 am
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Hi,

I want to design some circuits in virtuoso. Schematic and layout are included of my design. I need simulation libraries(5V nmos and pmos) of schematic, also layout technology files. How can i take these files? 

Thanks in advance.

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System Verilog outputs connected in parallel causes voltage division

July 13, 2020, 6:50 am
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Hi,

for functional verification we started to model our cells and top-level blocks in SystemVerilog.

For logic signals we are using the "logic' datatype.

For the analog signals we are using the 'real' datatype.

If  "logic" outputs are connected together, one can set all unused outputs hi-Z ("1'bz") and just have the one selected output drive the common output node.

But if "real" outputs are connected together, the interface elements (IE) are creating a voltage divider due to their finite output resistance.

The question is, if it is possible to declare a "real" output as high-Z or equivalent ?

And/or what is the better way to model "real-valued" parallel connected outputs ?

In my case I do have several DAC outputs in parallel. Each output has an internal transmission-gate to enable/disable the output. Only one DAC output is active at the time and drives/gives a "real" value to the output.

How to model this without getting a voltage divider due to parallel connection ?

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Error during Monte Carlo stimulation

July 13, 2020, 10:11 am
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I want to run a Monte-Carlo stimulation, but I get the error 'database disk image is malformed'. How can I solve this error? 

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Spectre stopping on symbol

July 14, 2020, 1:37 pm
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While generating a Spectre netlist, is there any way to force a cell to be netlisted as empty? I am planning to replace the cell with a separate .scs model file, but I need the connections to be made at the higher level.

I believe the normal method would be to create a 'spectre' cell view and use that as a stop point. However, I do not have write access to the library containing the cell. If I try to set the symbol view as the stop point, I get an error during Spectre netlisting:

    Netlist Error: Cannot find any info on instance "i0" in cell-view "library1" "cell1" "schematic"

I thought about trying to change the library via the config view / hierarchy editor, but that does not seem to be an option for schematic-based design data. I also tried using the "Specify SPICE source file" option in the hierarchy editor, but that is also giving the "Cannot find any info" error.

The only two options I can see remaining are: (1) copy the hierarchy so I can change to a different, writable, library, or (2) bind-to-open on this cell and postprocess/hack the generated netlist to add the connections myself

Am I missing anything here? Thanks!

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Importing Verilog-A code

July 14, 2020, 10:54 pm
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Hi All,

I wish you are well. 
I have imported a Verilog-A code of a specific model of a transistor in Cadence. I could create transistor symbol and run simulations for a few days. However, after a while, I saw this error once I tried to run the same simulations:
"Internal error found in spectre during AHDL read-in, during circuit read-in, during hierarchy flattening.

Encountered a critical error during simulation. Please run `mmsimpack' to pack the test case (use mmsimpack -h option to get detailed usage), and submit the case via Cadence Online Support, including the package tar file and any other information that can help identify the problem.
    FATAL (SPECTRE-18): Segmentation fault."

This is weird because it was working and, then, stopped suddenly. I wonder if anyone sees something like this before? And, is there any solution?
Cheers,
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apply jitter to oscillator model from external file

July 15, 2020, 12:49 am
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Hi,

I'm trying to add jitter to an oscillator model. The jitter (TIE) is based on a phase noise profile and is stored in a separate file. My thinking is that every oscillator edge, it reads the jitter file and add the next jitter value to the following cycle. 

I wonder if this is a good way to do it? Not sure by how much simulation will slow down with reading external file at 2x VCO frequency.

btw, is there a better way to generate jitter "on the fly" based on a known phase noise profile?

thanks,

Kevin

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unwanted symbol instance in the layout

July 15, 2020, 6:03 am
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Hello.

I am user of IC6.1.7 with GPDK180_v3.3.

From time to time when I started to run DRC, unexpected schematic symbols are added, which results in VDB error. 

Of course, when such a case occurs, I manually delete unexpected schematic symbol that I didn't add in the lay out to run drc in a normal way. But it feels cumbersome. 

I don't why such symbols, usually nmos or pmos(one or two), are added in the layout although I did nothing.

Do you have any answer?

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Error when doing Monte Carlo Simulation

July 15, 2020, 8:32 am
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Hi all,

I am doing Monte Carlo simulation with IC617 and TSMC 180nm PDK. I am using ADE explorer to do the simulation. But the simulation failed with the following error:

ERROR (EXPOLRER-5052): Monte Carlo run stopped because no statistical data generated for the test.

I ran different corners and it turned out that those simulations are running smoothly. But I am not sure about how to set model sections in MC simulation.

Here is how I set the MC model sections:

Basically I use typical mosfet, bipolar transistor and resistor to build a bandgap reference circuit. And I do set the the models to be those with mismatch characteristics. I think the model sections in the screenshot are enough to do the simulation.

Here is how I set the MC simulation:

Here is how I set the output signal:

Could someone please help me with it or give me some hint? 

Thanks in advance.

Best,

Orangehalo

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Fatal error when use ADE L to simulate veriloga blocks.

July 16, 2020, 10:08 am
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Hi,

I am using 6.1.6 to do some design and I try to use some VerilogA blocks, for example the blocks in ahdlLib and some customized blocks, in my simulation. But it meets an error showing below. The error index number is ' ERROR (VACOMP-1008)'. It seams that cadence cannot compile the ahdlcmi module library. I have no idea what is that.  I highlight the error message with red. Thank you very much if anyone can help me.

Simulating `input.scs' on sahand at 9:56:19 AM, Thur Jul 16, 2020 (process id: 2391).
Current working directory: /home/home2/students/haolinco/simulation/test_veriloga/spectre/schematic/netlist
Command line:
    /opt/cadence/MMSIM141/tools.lnx86/bin/spectre -64 input.scs  \
        +escchars +log ../psf/spectre.out +inter=mpsc  \
        +mpssession=spectre0_53396_1 -format psfxl -raw ../psf  \
        +lqtimeout 900 -maxw 5 -maxn 5
spectre pid = 2391

Loading /opt/cadence/MMSIM141/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /opt/cadence/MMSIM141/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ...
Loading /opt/cadence/MMSIM141/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /opt/cadence/MMSIM141/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /opt/cadence/MMSIM141/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file:  /home/home2/students/haolinco/simulation/test_veriloga/spectre/schematic/netlist/input.scs
Reading file:  /opt/cadence/MMSIM141/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading link:  /opt/cadence/IC616/tools/dfII/samples/artist/ahdlLib/and_gate/veriloga/veriloga.va
Reading link:  /opt/cadence/IC616/tools
Reading file:  /opt/cadence/IC616/tools.lnx86/dfII/samples/artist/spectreHDL/Verilog-A/logic/and_gate.va
Reading link:  /opt/cadence/MMSIM141/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading file:  /opt/cadence/MMSIM141/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Reading link:  /opt/cadence/MMSIM141/tools.lnx86/spectre/etc/ahdl/constants.h
Reading file:  /opt/cadence/MMSIM141/tools.lnx86/spectre/etc/ahdl/constants.vams

Warning from spectre during AHDL read-in.
    WARNING (VACOMP-2265): "$finish;<<--? "
        "/opt/cadence/IC616/tools/dfII/samples/artist/ahdlLib/and_gate/veriloga/veriloga.va", line 49: In Cadence Verilog-A, the $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.

Time for NDB Parsing: CPU = 94.71 ms, elapsed = 614.42 ms.
Time accumulated: CPU = 148.894 ms, elapsed = 614.434 ms.
Peak resident memory used = 66.4 Mbytes.


Warning from spectre during AHDL read-in.
    WARNING (VACOMP-2265): "$finish;<<--? "
        "/opt/cadence/IC616/tools/dfII/samples/artist/ahdlLib/and_gate/veriloga/veriloga.va", line 49: In Cadence Verilog-A, the $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.

Created directory input.ahdlSimDB/ (775)
Created directory input.ahdlSimDB//3712_artist_ahdlLib_and_gate_veriloga_veriloga.va.and_gate.ahdlcmi/ (775)
Created directory input.ahdlSimDB//3712_artist_ahdlLib_and_gate_veriloga_veriloga.va.and_gate.ahdlcmi/Linux-64/ (775)
Compiling ahdlcmi module library.

Warning from spectre during AHDL read-in.
    WARNING (VACOMP-2397): Compilation failed when using pipe build. Bytecode flow will be used for encrypted VerilogA, and normal file compilation will be used for unencrypted VerilogA.

Compiling ahdlcmi module library.

Error found by spectre during AHDL read-in.
    ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB//3712_artist_ahdlLib_and_gate_veriloga_veriloga.va.and_gate.ahdlcmi/Linux-64/../ahdlcmi.out for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. Otherwise, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.
    ERROR (SFE-91): Error when elaborating the instance and_gate. Simulation should be terminated.

Time for Elaboration: CPU = 64.186 ms, elapsed = 9.7813 s.
Time accumulated: CPU = 213.243 ms, elapsed = 10.3959 s.
Peak resident memory used = 75.2 Mbytes.


Aggregate audit (9:56:30 AM, Thur Jul 16, 2020):
Time used: CPU = 214 ms, elapsed = 10.4 s, util. = 2.05%.
Time spent in licensing: elapsed = 129 ms.
Peak memory used = 75.2 Mbytes.
Simulation started at: 9:56:19 AM, Thur Jul 16, 2020, ended at: 9:56:30 AM, Thur Jul 16, 2020, with elapsed time (wall clock): 10.4 s.
spectre completes with 2 errors, 3 warnings, and 0 notices.
spectre terminated prematurely due to fatal error.

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Error in abutment of transistor Pcells

July 16, 2020, 12:58 pm
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Hi,

I am getting the below message when trying to abut two transistor Pcells, inside a Modgen.

*WARNING* (LX-2206): Unable to abut the following two instances:
 'ModgenDummy_0_0_Modgen_1' (instance of cell 'egupfet_b')
 'P0' (instance of cell 'egupfet_b')
This occurred because the required abutment data is incorrect
or missing on the pin figures in the masters of these instances.
*WARNING* (LX-2206): Unable to abut the following two instances:
 'ModgenDummy_1_0_Modgen_1' (instance of cell 'egupfet_b')
 'P1' (instance of cell 'egupfet_b')
This occurred because the required abutment data is incorrect
or missing on the pin figures in the masters of these instances.
.

Please let me know a possible reason for this error.

Thanks,
Mallikarjun

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Pnoise can not plot Jc(k)

July 16, 2020, 1:29 pm
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Hi,

I have done the PSS and Pnoise simulation of a RC oscillator. I want to use Jc(k) function to show the cycle jitter as below

But cadence shows me the error, saying unable to plot expression ...

I expect your support. My cadence version is IC618. 

BR

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Update PCELL Parameters in APR

July 17, 2020, 6:55 am
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Can I get more clarifications on the option " Update Pcell Params " in Auto P&R?

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PSD Calculation of a Pulse Train after a Transient Simulation

July 19, 2020, 2:44 pm
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Dear Community,

I performed a very simple PSD calculation for a periodic pulse train that is generated using Verilog-A modelling. The pulse train has fixed high voltage 1V and low voltage 0V, fixed duty cycle of 50%, and fixed frequency of 1s. I ran the Transient Noise simulation using ADE L for 1000s (usingt Transient Noise analysis in order to directly acquire ADE L -> result -> main form -> PSD once the simulation finishes). Below are the signal waveform and transient noise simulation setting: 

The PSD calculation expression is therefore: db10(psd(VT("/M") 1 993 198400 ?windowName "Rectangular" ?smooth 1 ?windowSize 12400 ?detrending "None" ?cohGain 1))

However, after calculation, I got the spectrum as shown below, which has the frequency-domain spikes with height 10.99dB at fundamental (1Hz) and 1.45dB at 3rd harmonic (3Hz) and so on, which is counter-intuitive. Because theoretically for a standard 50%-duty-cycle pulse train the PSD at fundamental should be 10log(Cn^2)=10log(0.3183^2) = -9.94dB and at 3rd harmonic 10log(0.1061^2) = -19.49dB, and so on.

Is there anything incorrect with my method of acquiring the power spectrum?

Also, I tried to perform the PSD calculation using the same method (but updated simulation time and sampling frequency, etc.) setting the 50%-duty-cycle pulse train frequency to 100Hz and 10kHz. But the frequency tones at all the harmonics are -20dB and -40dB lower throughout the spectrum compared with the 1Hz case. Why is that (should the heights at the corresponding harmonics not be the same for those three cases)?

Many thanks!

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Create VDR Labels/Markers from Simulation Voltages

July 20, 2020, 9:41 am
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I am trying to use the simulation-based Voltage Dependent Rules (VDR) flow for the 1st time.
Question: If I saved the Vmin/Vmax dataset from a EAD-enabled simulation of a TB, it creates 'constraint' view for the DUT. Why is that when the DUT layout view is opened in Layout XL, invoking Tools > VDR... > Create Labels/Voltages from Simulation Voltages...  The VDR form does not show any simulation datasets, even after clicking the Update button?

My Virtuoso version is ICADVM18.1 isr10.

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low voltage SRAM Design

July 20, 2020, 12:44 pm
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I am working on project and i need help regarding this topic:

"Evaluation of Low Voltage Performance Enhancement techniques in SRAMs  and its physical design (with annotated capacitances)"

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