I have a verilog code. I want to dump the code in Cadence Virtuoso and use the instance in my design. what is the procedure for it?

I want to run simulations without Explorer creating a new netlist, but it doesn’t seem keen.

I thought hitting run instead of netlist and run was sufficient, but it re-creates the netlist every time. I can’t find a way to tell it not to do that.

I've also tried creating a netlist for the circuit under test and used the config view to point to the netlist instead of the schematic, but I  get duplicate definition errors, an if I remove the duplicate definitions I am left with an error that it doesn't have a definition of the subcircuit I'm trying to simulate.

I feel the solution to this should be easy.

Hi,

I have 3 cells as:

Cell_A with views schematic and symbol
Cell_B with views veriloga and symbol
Cell_C with views schematic, veriloga and symbol.

In the top cell I use the 3 cells and with the config file I select the view veriloga for the Cell_C

The issue is that the netlist doesn't add the Cell_C verilog view.

In the config file I have:
View List: spectre cmos_sch cmos.sch schematic veriloga ahdl pspice dspf
Stop List: spectre

The warning message shown is:

WARNING (OSSHNL-117): Ignoring switch view 'veriloga' of cell 'Cell_C' in library 'test_library', as it does not contain
any instance. To netlist this cell, add this switch view to the stop list or to
ignore any specific instance set the property 'nlAction' to value "ignore" on
this cell view.

Any idea how can I solve it?
I know that in ADE L, in the environment is possible to update the switch view list, but I can not find it in the ADE XL

Best regards,

Eduard

Hi, everyone,

    I need some help for generating LIb with Liberate. The error reminder include

WARNING (LIB-411): An estimated max load value of 2.98572e-14F will be used for pin: 'Z' of cell: 'INVM0R' because the auto_index algorithm failed to determine the max load using bisection. This can occur when the inside-view algorithm cannot determine a valid vector. Add appropriate 'define_arc' commands specific to pin 'Z' and rerun.

INFO: Write Liberty
LIBERATE parameter "mx_format_expand_buses" set to "0"
LIBERATE parameter "ecsm_multi_stage_cap_mode" set to "0"
LIBERATE parameter "ccsp_mode" set to "0"
LIBERATE parameter "enable_command_history" set to "0"

*Error* (char_library) : Bad ccs data found in #0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ccs vector for cell:INVM0R, pin:Z, related_pin:A, when:"". This timing group will be skipped!!
*Error* (char_library) : Bad ccs data found in #0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ccs vector for cell:INVM0R, pin:Z, related_pin:A, when:"". This timing group will be skipped!!

I'm confused that the information show there is no failling cell, but the error information occurs at "Write Liberty"

Characterization statistics:

Number of cells to characterize = 1
Number of define_cell commands = 3
Number of passing cells = 1
Number of failing cells = 0

Could someone give me some suggestions? I'm so grateful.

Hi ,

I had a question regarding PVS LVS rules writing behavior. I have a deck from foundry which has some code in the following manner :

not A B -output A1

not A B -output A2 

not A B -output A3 

i.e. same layers with same operation resulting in three different output layers. I ran LVS with Layer viewer and I can see only the A1 layer in the layer viewer. 

Now my question is why I do not see A2 and A3? Could it somehow be dependent on operations that happen next  on A1,A2 and A3? Would this also happen if the operation was something else (like AND)? 

Regards

Suryansh Singh

Hi all.

I'm simulating a Voltage Reference with startup circuit and I'm having DC operating point differences between transient steady state and DC Op calculation. The simulator found an operating point different from 0 and desirable transient steady state value. I have tried to solve it setting some nodesets specifically in the startup and PMOS mirror gate and also change the homotopy option to dptran and ptran without success.

Could anyone give me some hint or trick to get an adequate DC operating point?

Thanks in advance!

Hello,

We are using the TSMC 180um for a low power project in our group. Now we are going to do a post-layout simulation for our design. Still, unfortunately, we see that we haven't access to the front-end (Schematics) files of Input/output (IO) cells in IO libraries. I contact by their support in Europractice (Imec). They said we could not access front-end information till tape-out time.  

Is there anyone that has worked by TSMC PDKs and have the same problem? If we cannot access those files cause of some protection issue of TSMC company with university licenses, Please let me know how we can do LVS check or post-layout simulation? 

Best,

Hi,

I want to generate a random number between -1 and 1 in Verilog-A by using "$rdist_uniform" or "$random", but the behaviour is not as I expect it.

My code is something like:

@ ( initial_step ) begin

for (1=0; i<10; i=i+1) begin

   myvar[i]= $rdist_uniform(seed,-1,1)

end

end

When "seed=123" ( a constant) i always get the same value in myvar[0:9].

When "seed=i" the values in myvar[0:9] are increasing linearily.

I am missing the "randomicity" in the values.

If I would need to scramble the seed, I also could use the scrambled value instead of the random function.

How can I generate randomly distributed values ?

Hi everyone,

I'm fairly new to Cadence so I'm sorry if this is easily solvable.
I am trying to generate a symbol with a variable parameter. For instance, I have an inverter with the NMOS width set to : pPar("width") and the PMOS width set to: 2*pPar("width").

I have gone through the CDF window to edit the parameter using the base CDF layer. (See picture for reference)

Here is the schematic of my simple design:

And here is the schematic using the instantiated inverter as a symbol:

When I try to run a simple simulation using Spectre, I get the following error:

I am wondering what I am doing wrong.

Edit: All schematic have been compiled and checked by the Virtuoso schematic editor with no errors or warnings.

Thank you very much for your help,

Alexandre Boyer

Hello Everyone,

I am having trouble of late trying to print out noise summary reports following a Spectre noise analysis.

The following problems seem to show up:

1) Noise contributors aren't printing correctly for the full hierarchy tree even though I am not selecting a particular hierarchy level when printing the noise summary.

I am forced to select hierarchy level to something, e.g. "1" or "2" etc. else some noise contributors are printed but with zero contribution.
This is obviously not right since the items printed would make a significant nonzero contribution, but is likely due to the next problem, which is:

2) Noise contributor numbers shown are unreasonably and impossibly large, e.g. 10^27 V^2.
The percentage noise contributions (which by definition cannot exceed 100) are also astronomically large, e.g. 10^30 %.

The total summarized noise is perfectly in order. So, it's not as if there is some modelling issue that might cause the noise to blow up in simulations.

Given that I wasn't seeing any of the above problems until recently and there has been no change to either my Spectre binary release or to the models anytime in the last several weeks, I am guessing that there must be a rogue setting somewhere causing things to go wrong.

Does anyone have an idea what the cause and resolution might be? The noise summary as it is now is totally unusable.

I am using spectre release 19.10.063.

Thanks,
Vivek

Hi, I have 3 tests I want to run. The first test is a calibration that I run at just 50 degrees.

Test2 and Test3 are the same but with different input current, both are swept across temperature.

In test2 I calculate an output across temperature using the calibrated value from test1 at each temperature by using calcVal("parameter" "testName" ?getfirstSweepPoint t).

I then want to pass an output of test2 to test3 at each individual temperature point. I have tried using calcVal("parameter" "testName" ?mtachParams "all") and calaVal("parameter" "testName" ?matchParams list(list("temperature" "-40") list("temperature" "-30"))) but I always get an eval error in test3. Any tips to what I am doing wrong?

Hi,

When performing the LVS , I am getting this error.

ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'auCdl schematic', for the
instance 'output_1_reg[0]' in cell 'New_ALU'. Either add one of these views to the library 'FINAL',
cell 'dff' or modify the view list to contain an existing view.

Following is the content of my dff cell. 

Can anybody help me in debugging this. 

Hi all,

 I've started encountering a problem with corner plots. I usually can plot a value across corners, and it connects the dots into a line. Right now I just get separate dots. It seems it just plots separate expression for each corner value.

Is there any command I can run to fix this?

BR,

Roman K.

Dear All,

I was running a testbench in ADE with AMS engine. It had vHDL and verilogA modules. It was running fine.

But when I removed the verilogA module (i.e. DCO present in VERILOG_A_MODULE_2 library) it shows the following error and simulation doesn't run.

ncvlog: *E,WKLNDF (./INCA_libs/AMSD/ahdl_in/generated_skeleton_ahdl.skl_vams,191|27): library 'VERILOG_A_MODEL_2' is not defined.
module worklib.DCO:veriloga
errors: 0, warnings: 0
Total errors/warnings found outside modules and primitives:
errors: 1, warnings: 5.

Can anybody please tell how to fix this issue.

Kind Regards,

Hello,

There is a similar question posted here https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/40093/matlab-cds_srr-dc-sweep-of-mosfet-parameters

I would like to run a 4-dimensional DC sweep and noise analysis in Cadence spectere via Matlab by calling the simulator via a Linux command line. I have two Matlab scripts,  the main and the configuration scripts. The first script is the main script which doesn’t include the user or process-specific parameter. It creates a two-dimensional for-loop of the length and the source to bulk voltage. For each value of the sweep, Matlab writes a new netlist and calls the simulator via the Linux command line which then runs the inter 2-D sweep of VGS and VSB. For each iteration, the result is read back to Matlab via cds_srr function which is provided by the Cadence specter toolbox. After each simulation run is completed, then the data set is stored in the lookup table output file. And within in Matlab script, this data can be loaded. The second script is the configuration script that has n several sections such as:

defining the file path to the simulator

defining the sweep ranges and sweep size

defining the syntax template for netlist

mapping the simulator output variable to the Matlab variable.

When I run the main script by launching Matlab within the command line, where all necessary model files are located, I get the error saying that Simulation did not run properly.  The generated netlist file called techsweep.scs is provided below. What I am I doing wrong? Normally within ADEXL GUI The model files are defined as follows

Global model files:

design.scs

wafer.scs

model.scs tt

Which are also highlighted in yellow below for clarity.

What should I put for models in c.modelfile = ‘.<> in the second script? I just did c.modelfile = './models

The netlisttechsweep.scs, gnerated by  the Main Matlab script is shown below:

//techsweep.scs

include "./models"

include "techsweep_params.scs"

include "./models/design.scs"

include "./models/wafer.scs"

include "./models/allModels.scs" section=tt

save mn.m1.m1

save mn.d1.d1

save mn.d2.d1

save mp.m1.m1

save mp.d1.d1

save mp.d2.d1

parameters gs=0 ds=0

vnoi     (vx  0)         vsource dc=0 

vdsn     (vdn vx)        vsource dc=ds 

vgsn     (vgn 0)         vsource dc=gs 

vbsn     (vbn 0)         vsource dc=-sb

vdsp     (vdp vx)        vsource dc=-ds

vgsp     (vgp 0)         vsource dc=-gs

vbsp     (vbp 0)         vsource dc=sb 

mn       (vdn vgn 0 vbn) nch  l=length w=10 nfing=5

mp       (vdp vgp 0 vbp) pch  l=length w=10 nfing=5

simOptions options gmin=1e-13 reltol=1e-4 vabstol=1e-6 iabstol=1e-10 temp=27 tnom=27 rawfmt=psfbin rawfile="./techsweep.raw"

sweepvds sweep param=ds start=0 stop=1.200000e+00 step=2.500000e-02 {

   sweepvgs dc param=gs start=0 stop=1.200000e+00 step=2.500000e-02

}

sweepvds_noise sweep param=ds start=0 stop=1.200000e+00 step=2.500000e-02 {

   sweepvgs_noise noise freq=1 oprobe=vnoi param=gs start=0 stop=1.200000e+00 step=2.500000e-02

}

The main Matlab script

clearvars;
close all;

% Load configuration

c = techsweep_config_psp_120_spectre;

% Write sweep info
nch.INFO = c.modelinfo;
nch.CORNER = c.corner;
nch.TEMP = c.temp;
nch.NFING = c.NFING;
nch.L = c.LENGTH';
nch.W = c.WIDTH;
nch.VGS = c.VGS';
nch.VDS = c.VDS';
nch.VSB = c.VSB';
%
pch.INFO = c.modelinfo;
pch.CORNER = c.corner;
pch.TEMP = c.temp;
pch.NFING = c.NFING;
pch.L = c.LENGTH';
pch.W = c.WIDTH;
pch.VGS = c.VGS';
pch.VDS = c.VDS';
pch.VSB = c.VSB';

% Simulation loop
for i = 1:length(c.LENGTH)
str=sprintf('L = %2.3f', c.LENGTH(i));
disp(str);
for j = 1:length(c.VSB)
% Write simulation parameters
fid=fopen('techsweep_params.scs', 'w');
fprintf(fid,'parameters length = %d\n', c.LENGTH(i));
fprintf(fid,'parameters sb = %d\n', c.VSB(j));
fclose(fid);

pause(5)

% Run simulator
[status,result] = system(c.simcmd);
if(status)
disp('Simulation did not run properly. Check techsweep.out.')
return;
end

% Initialize data blocks
for m = 1:length(c.outvars)
nch.(c.outvars{m})(i,:,:,j) = zeros(length(c.VGS), length(c.VDS));
pch.(c.outvars{m})(i,:,:,j) = zeros(length(c.VGS), length(c.VDS));
end

% Read and store results
for k = 1:length(c.n)
params_n = c.n{k};
struct_n = cds_srr(c.outfile, c.sweep, params_n{1});
values_n = struct_n.(params_n{2});
params_p = c.p{k};
struct_p = cds_srr(c.outfile, c.sweep, params_p{1});
values_p = struct_p.(params_p{2});
for m = 1:length(c.outvars)
nch.(c.outvars{m})(i,:,:,j) = squeeze(nch.(c.outvars{m})(i,:,:,j)) + values_n*params_n{3}(m);
pch.(c.outvars{m})(i,:,:,j) = squeeze(pch.(c.outvars{m})(i,:,:,j)) + values_p*params_p{3}(m);
end
end
% Noise results
for k = 1:length(c.n_noise)
params_n = c.n_noise{k};
% note: using cds_innersrr, since cds_srr is buggy for noise
struct_n = cds_innersrr(c.outfile, c.sweep_noise, params_n{1},0);
field_names = fieldnames(struct_n);
values_n = struct_n.(field_names{4});
params_p = c.p_noise{k};
% note: using cds_innersrr, since cds_srr is buggy for noise
struct_p = cds_innersrr(c.outfile, c.sweep_noise, params_p{1},0);
field_names = fieldnames(struct_p);
values_p = struct_p.(field_names{4});
nch.(c.outvars_noise{k})(i,:,:,j) = squeeze(values_n);
pch.(c.outvars_noise{k})(i,:,:,j) = squeeze(values_p);
end
end
end

save(c.savefilen, 'nch');
save(c.savefilep, 'pch');

The configeration Matlab script: 

function c = techsweep_config_psp_120_spectre

% Models and file paths
c.modelfile = './models';
c.modelinfo = '120nm CMOS, PSP';
c.modeln = 'nch';
c.modelp = 'pch';
c.simcmd = 'set path=($path /apps/cds/ic618/tools/bin); /apps/cds/spectre181/tools/bin/spectre techsweep.scs >! techsweep.out';
c.outfile = 'techsweep.raw';
c.sweep = 'sweepvds_sweepvgs-sweep';
c.sweep_noise = 'sweepvds_noise_sweepvgs_noise-sweep';

% Corner dependent parameters
c.corner = 'NOM';
c.temp = 300;
c.savefilen = '120nch';
c.savefilep = '120pch';

end

% Sweep parameters
c.VGS_step = 25e-3;
c.VDS_step = 25e-3;
c.VSB_step = 0.1;
c.VGS_max = 1.2;
c.VDS_max = 1.2;
c.VSB_max = 1.0;
c.VGS = 0:c.VGS_step:c.VGS_max;
c.VDS = 0:c.VDS_step:c.VDS_max;
c.VSB = 0:c.VSB_step:c.VSB_max;
c.LENGTH = [(0.12:0.01:0.2) (0.25:0.05:1)];
c.WIDTH = 10;
c.NFING = 5;

% Variable mapping
c.outvars = {'ID','VT','IGD','IGS','GM','GMB','GDS','CGG','CGS','CSG','CGD','CDG','CGB','CDD','CSS'};
c.n{1}= {'mn.m1.m1:ids','A', [1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]};
c.n{2}= {'mn.m1.m1:vth','V', [0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]};
c.n{3}= {'mn.m1.m1:igd','A', [0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]};
c.n{4}= {'mn.m1.m1:igs','A', [0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ]};
c.n{5}= {'mn.m1.m1:gm','Ohm', [0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]};
c.n{6}= {'mn.m1.m1:gmb','Ohm', [0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]};
c.n{7}= {'mn.m1.m1:gds','Ohm', [0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]};
c.n{8}= {'mn.m1.m1:cgg','F', [0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]};
c.n{9}= {'mn.m1.m1:cgs','F', [0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ]};
c.n{10}={'mn.m1.m1:cgd','F', [0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 ]};
c.n{11}={'mn.m1.m1:cgb','F', [0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ]};
c.n{12}={'mn.m1.m1:cdd','F', [0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ]};
c.n{13}={'mn.m1.m1:cdg','F', [0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ]};
c.n{14}={'mn.m1.m1:css','F', [0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]};
c.n{15}={'mn.m1.m1:csg','F', [0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]};
c.n{16}={'mn.m1.m1:cgsol','F', [0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 ]};
c.n{17}={'mn.m1.m1:cgdol','F', [0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 ]};
c.n{18}={'mn.m1.m1:cgbol','F', [0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 ]};
c.n{19}={'mn.d1.d1:cj','F', [0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ]};
c.n{20}={'mn.d2.d1:cj','F', [0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]};

% {'ID','VT','IGD','IGS','GM','GMB','GDS','CGG','CGS','CSG','CGD','CDG','CGB','CDD','CSS'};
c.p{1}= {'mp.m1.m1:ids','A', [1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]};
c.p{2}= {'mp.m1.m1:vth','V', [0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]};
c.p{3}= {'mp.m1.m1:igd','A', [0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]};
c.p{4}= {'mp.m1.m1:igs','A', [0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ]};
c.p{5}= {'mp.m1.m1:gm','Ohm', [0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]};
c.p{6}= {'mp.m1.m1:gmb','Ohm', [0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]};
c.p{7}= {'mp.m1.m1:gds','Ohm', [0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]};
c.p{8}= {'mp.m1.m1:cgg','F', [0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]};
c.p{9}= {'mp.m1.m1:cgs','F', [0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ]};
c.p{10}={'mp.m1.m1:cgd','F', [0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 ]};
c.p{11}={'mp.m1.m1:cgb','F', [0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ]};
c.p{12}={'mp.m1.m1:cdd','F', [0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ]};
c.p{13}={'mp.m1.m1:cdg','F', [0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ]};
c.p{14}={'mp.m1.m1:css','F', [0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]};
c.p{15}={'mp.m1.m1:csg','F', [0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]};
c.p{16}={'mp.m1.m1:cgsol','F', [0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 ]};
c.p{17}={'mp.m1.m1:cgdol','F', [0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 ]};
c.p{18}={'mp.m1.m1:cgbol','F', [0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 ]};
c.p{19}={'mp.d1.d1:cj','F', [0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ]};
c.p{20}={'mp.d2.d1:cj','F', [0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]};
%
c.outvars_noise = {'STH','SFL'};
c.n_noise{1}= {'mn.m1.m1:Sth', ''};
c.n_noise{2}= {'mn.m1.m1:Sfl', ''};
%
c.p_noise{1}= {'mp.m1.m1:Sth', ''};
c.p_noise{2}= {'mp.m1.m1:Sfl', ''};

% Simulation netlist
netlist = sprintf([...
'//techsweep.scs \n'...
'include "%s" \n'...
'include "techsweep_params.scs" \n'...
'include "./models/design.scs" \n'...
'include "./models/wafer.scs" \n'...
'include "./models/allModels.scs" section=tt \n'...
'save mn.m1.m1 \n'...
'save mn.d1.d1 \n'...
'save mn.d2.d1 \n'...
'save mp.m1.m1 \n'...
'save mp.d1.d1 \n'...
'save mp.d2.d1 \n'...
'parameters gs=0 ds=0 \n'...
'vnoi (vx 0) vsource dc=0 \n'...
'vdsn (vdn vx) vsource dc=ds \n'...
'vgsn (vgn 0) vsource dc=gs \n'...
'vbsn (vbn 0) vsource dc=-sb \n'...
'vdsp (vdp vx) vsource dc=-ds \n'...
'vgsp (vgp 0) vsource dc=-gs \n'...
'vbsp (vbp 0) vsource dc=sb \n'...
'mn (vdn vgn 0 vbn) %s l=length w=%d nfing=%d \n'...
'mp (vdp vgp 0 vbp) %s l=length w=%d nfing=%d \n'...
'\n'...
'simOptions options gmin=1e-13 reltol=1e-4 vabstol=1e-6 iabstol=1e-10 temp=%d tnom=27 rawfmt=psfbin rawfile="./techsweep.raw" \n'...
'sweepvds sweep param=ds start=0 stop=%d step=%d { \n'...
' sweepvgs dc param=gs start=0 stop=%d step=%d \n'...
'}\n'...
'sweepvds_noise sweep param=ds start=0 stop=%d step=%d { \n'...
' sweepvgs_noise noise freq=1 oprobe=vnoi param=gs start=0 stop=%d step=%d \n'...
'}\n'...
], c.modelfile, ...
c.modeln, c.WIDTH, c.NFING, ...
c.modelp, c.WIDTH, c.NFING, ...
c.temp-273, ...
c.VGS_max, c.VGS_step, ...
c.VDS_max, c.VDS_step, ...
c.VGS_max, c.VGS_step, ...
c.VDS_max, c.VDS_step);

% Write netlist
fid = fopen('techsweep.scs', 'w');
fprintf(fid, netlist);
fclose(fid);

return

Alternatively, I could just edit the teschsweep.scs in a text editor and remove the ./ model and add the length and the model manually as follows:

//techsweep.scs
include "techsweep_params.scs"
include "./models/design.scs"
include "./models/wafer.scs"
include "./models/allModels.scs" section=tt
save mn.m1.m1
save mn.d1.d1
save mn.d2.d1
save mp.m1.m1
save mp.d1.d1
save mp.d2.d1
model nch psp103 type=n
model pch psp103 type=p
parameters gs=0 ds=0
vnoi (vx 0) vsource dc=0
vdsn (vdn vx) vsource dc=ds
vgsn (vgn 0) vsource dc=gs
vbsn (vbn 0) vsource dc=-sb
vdsp (vdp vx) vsource dc=-ds
vgsp (vgp 0) vsource dc=-gs
vbsp (vbp 0) vsource dc=sb
mn (vdn vgn 0 vbn) nch l=0.12u w=10 nfing=5
mp (vdp vgp 0 vbp) pch l=0.12u w=10 nfing=5

simOptions options gmin=1e-13 reltol=1e-4 vabstol=1e-6 iabstol=1e-10 temp=27 tnom=27 rawfmt=psfbin rawfile="./techsweep.raw"
sweepvds sweep param=ds start=0 stop=1.200000e+00 step=2.500000e-02 {
sweepvgs dc param=gs start=0 stop=1.200000e+00 step=2.500000e-02
}
sweepvds_noise sweep param=ds start=0 stop=1.200000e+00 step=2.500000e-02 {
sweepvgs_noise noise freq=1 oprobe=vnoi param=gs start=0 stop=1.200000e+00 step=2.500000e-02
}

and do:

spectere teschsweep.scs and

it works. But what I want is for the main Matlab script to call the simulator via the Linux command line.

Thanks for all your help.

Hi,

I want to write a Verilog-A module in which I use the instantaneous-power-consumption of another module (a subcircuit, say called "DUT") as a variable.  How can I do that?

"DUT" is somewhat complex, so it will be preferable for me to make use of the buit-in "DUT:pwr" or some such expression if possible, rather than sum the instantaneous V*I of all terminals of DUT.

Regards,

Vipul

Dear All,

I was simulating a VHDL module in AMS with plot in VIVa.

The module looks like as at the end of this post.

If deltat_rec value is same at nth, n+1th rising edge of clock signal 'clk', the wavescan plot  ( in SampleHold  trace format ) of signal deltat_rec does have a point at nth rsing edge but NOT at  n+1th rising edge.

Is there any we can ensure that the WaveScan plot doesn't miss n+1th point so that when we will export the trace, the file will have n+1th point.

Kind Regards,

deltat_proc:process(clk)
begin
if (clk='0') and (clk' event) then
deltat_rec <= delta_t;
end if;
end process deltat_proc;

Hi,

I am trying to define a custom function (analog function) that takes a string input and returns a string;

analog function integer foo;

   input strin;

   output strout;

   string strin; 

    string strout;

  begin 

       strout = {strin,strin};

end

endfunction

string output_str;

analog begin

 @(initial_step) 

      foo("bar", output_str);

end

This yields an error during similar to:

ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file /…./…/Sim/… … /adexl/results/data/Interactive.33/sharedData/CDS/ahdl/input.ahdlSimDB/24626ad5616da27e0a69c18e90226eba.bias_autotrim.ahdlcmi/Linux-64//..//ahdlcmi.out for details. Contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.

    ERROR (SFE-91): Cannot run the simulation because an AHDL compilation error occurred. Check the VACOMP error message above and correct the syntax error in the Verilog-A file. Next, rerun the simulation.

Investigating the ahdlcmi.out file, the first encountered error is:

aslDevAssignStringC(2, &stateDataStruct->input_str_144,(char*)stateDataStruct->input_str_152, funcModeParam);

                        ^

In file included from test.c:24:0:

/mnt/ed/ct/lnx/rh/53/64/…/spectre/tools.lnx86/spectre/ahdlcmi/include/ahdlDevLibGlobal.h:2390:32: note: expected 'char *' but argument is of type 'long int *'

 ASL_FUNC_DECL_START extern int aslDevAssignStringC( int, char *, char *, struct ahdlFuncModeParam * );

I guess this is some intermediate compilation message (VerilogA->C), but I couldn’t get further investigating it.

Interestingly, removing the strout output parameter from the function and leaving only an input string works just fine.

What could be a possible solution to this issue?

Cheers,

Dimitar

Hello 

I would like to know how to kill PVS floating licenses. Only the license number is available e.g. lcl01/1000 .

Thank you in advance.

Hi,

I need to access a variable of instance from within the parent module in VerilogA. Something like this:

module child;

      integer child_int;
// some code
//....

endmodule

module parent;

     child my_child;

  analog begin
      @(initial_step) 
           $display(“Child_int value : %d”, my_child.child_int);
  end     

endmodule      

This example results in the following error during extraction:

Error found by spectre during AHDL compile.

    ERROR (VACOMP-2162): "$display("Child_int value %s", my_child.child_int<<--?

        ); "

        "/home/……./projects/……/veriloga/veriloga.va",

        line 124: Encountered a hierarchical name that is either incomplete or

        unsupported. Specify the hierarchical name as :

        [ instance_name{.instance_name}.]HDL_Instance_name

Searching through the Cadence VerilogA LRM doesn’t really give any hint. So what am I missing?

Thanks and best regards,

Dimitar