Is there a way to temporarily hide/unhile certain subwindows in a ViVA plot for version ICADV18.1? In ViVA ICADV12.3, there was a subwindow assistant that does so, but the plot layout changed in 18.1 and this feature isn't found in the new GUI.
Thanks.
Hi,
I am trying to optimize my design using cadence ocean script to print a results on text file and then I am using Matlab for post processing this results and do iterations. The first criteria I have is to check whether the operating region of Transistor is in saturation or not "if(Region==2)". For 1-dimensional sweep I used to do it by writing "save MP:all" in text file and adding the path in stimulusFile and using using getData("MP:region" ?result "dc") to get transistor operating region.This method works very well in 1-dimensional sweep, however, I tried to use the same way for 2-dimensional sweep and it was not helpful. Does anybody know a way of checking transistors operating region in multi-dimensional sweep?
Thanks in advance,
Ata
I have a CMOS inverter that I've extracted to a dspf file using Calibre xACT.
When I save any of the terminal currents of the extracted block in a harmonic balance simulation, the circuit ceases to oscillate and the output is just a dc signal.
Does anyone know why this happens? The simulation completes without error and it was just luck that I noticed this was the cause. I've tried it with transient and dc simulations but they run fine.
I'm using Cadence ICADVM18.1-64b.83.
Hello,
I am intersecting two signals by using Intersect function from ADE calculator and reading the intersection point as text (x,y) then I push it to my ADE to be saved for the next run. However, when I repeat the simulation this intersection point will appear as a point in the resulting graph.
How can tell the ADE to present it as data text?
I am using ADE L, Spectre Simulator version 11.1.0.509 2012 using
Thank you
Dear all,
there is a similar post from about 2 years ago, addressing the same problem (but for AMS Designer), but not offering a solution to immediately work (in my case ADE-L and Spectre).
I would like to export all design variables of an ADE-L session (later maybe also ADE Explorer) for reasons of documentation. For Outputs, there is an Export (and Import) command, but not for Variables.
1) The ideal solution would be two menu commands, Variables/Export... and Variables/Import..., that will save or load the variables into/from a CSV file. Then I could use such file for both documentation and (selective) import into a different session.
2) As currently, there is no such command, some SKILL code would help out (to be written into a file and started from CIW by loading the file). Andrew Becket mentions a "asiGetDesignVarList(asiGetCurrentSession())" SKILL command that should help here, yet it only results in an error (when entered in CIW, but maybe that is the wrong place): *Error* asiGetDesignVarList: no applicable method for the class - list()
So, if anyone has any solution for this, it would be great to share it in this forum...
Thank you very much.
Hello,
I am running the Circuit optimization from ADE GXL, I am practising simple two-stage operational amplifier as it has shown below,
I want to include a formula in my output setup the M6 drain current is near or equal to M7 drain current. This condition for the optimizer will assure that my circuit will have a very small offset voltage.
It is very basic to bring both currents to the output setup but I don't know how to make this expression formula between them,
Thank you
Hello
I would like to ask you how can I run a different type of simulation in one simulation environment, for example suppose I want to do the basic simulation of op-amp like
-input common mode range
-AC performance
-transient performance
-open loop response
-etc
I usually run every simulation individually in a separation schematic file,
However, right now I am keen to use the circuit optimization from ADE GXL to optimize my design, if I run the optimizer for the AC performance then he might degrade the transient and so on, therefore I need to include all type of simulation to be checked by the optimizer so it can find the solution tha satisfy all the specifications
am using ADE L, Spectre Simulator version 11.1.0.509 2012
and Cadence Virtuoso IC6.1.5-6b bit
Thank you very much
Hello,
I usually run multiple simulations at the same time and use ocean script to do that. If I want to view the plots after, I view it in ADEXL environment. If I want to quickly run interactively after, I am neither able to edit the output setup nor able to view the test editor in ADE XL.
1) Could you please let me know why this is happening?
2) Is there an option to change the test editor from Ocean to ADEXL in an interactive run, following an ocean run?
Thanks in advance,
Krithika
Hi All,
Usually, when hoving the mouse over a button, a menu or a blank space to fill, a rectangle information balloon popup to provide information about the function or what information is expected when filliing a form.
I'm using 6.1.7, and in the current setting the background color is pink and the text is white so that the information are completely unreadable. (pic below)
Does anyone knows where to modify this background color?
Thank you
Regards
KC
Hi,
I'm trying to migrate from Assura extraction to PVS. Tool versions:
IC6.1.7
Assura41.6
PVS191
EXT191
I have LVS decks which were supplied by the fab (e.g. TSMC65nm GP), and both PVS and Assura LVS work fine (i.e. clean cell, no funny log errors).
However, when running QRC with the Assura database it runs fine (again, no funny errors, result makes sense etc) but PVS-QRC terminates with the following error:
"There was no library cell mapping file (extview.trp (V2) or icellmapfile.yaml), or alternatively the extview"
What is happenning? I did some reading and it seems like the fab should give me either of the missing files. But then - how is Assura-QRC working? And if it does - Is there a way to retreive the missing information from the Assura deck files?
I'm in contact with the fab but this might be lengthy. In the meantime any help will be much appreciated.
Thanks!
Matan
hello sir, when i draw the layout of the buffer circuit, there is no DRC error but there is one LVS error that occurred which is related to unbound pin.i attached the image of my layout, in this image the highlighted part shows the error. 
Dear all：
I transfer layout from tsmc18 to smic18 with VLM tools. As shown in the figure below, the VLM flow indicates that migration works successfully. and I checked my setups, there seems to be no problem with the settings as shown in the following figures. but the instances in transformed layout view is not at correct place. Is there a problem with my setup and how to solve it ?
thx for your reply
Hello,
I have recently worked with Circuit optimization using Cadence ADE GXL. I used both the Global and the Local optimizer to final size my circuit against PVT corners, seems everything is ok for me. I read in Cadence documentation help about the Feasibility Analyses, but I didn't understand the purpose of it or what is the difference between it and the global or local optimization?
Anyway, I have tried to run it and see it but I am receiving this error message,
I kindly need your help to solve this issue and to understand the purpose of running the Feasibility analyses
Thank you
Hi,
From this link:
it was recommended to use shooting for circuitry that has sharp transitions, but hb for circuitry that has s-parameters.
My circuit has a series of buffers (sharp edge) and also s-parameter to reflect some routing so I tried both shooting and harmonic balance. I did not notice significant difference in pss sim itself, but hb take much less time for noise analysis(i use the same no. of harmonics). Is there a reason why?
The other observation, is that noise analysis result on the nodes along the chain of buffers are the same between hb and shooting, but for the nodes before and after sp file, they are quite different. Since hb is recommended for sp model, does that mean we should trust result from hb instead of shooting? in other words, it's more an accuracy concern than efficiency ?
thanks,
Kevin
Hi
i would like to know if I can introduce delay on transient signal by calculator function or expression.
Hi,
I am using Virtuoso ADE Assembler for post-layout simulation. And the version is ICADV12.3-64b.main.957.
My steps is following
1)I set "save all", ran post-layout sim (transient sim) and get the signal expression from result browser as below,
v("/i0/Xith0/Xi0/Xthpsf_combo/Xampp/Xth_psf/Xth_sw[0]/Mpassgate2[0]:SRC" ?result "tran").
2) Put the expression in "Outputs Setup", changed Output Save setup back to "Select". Reran the post-layout sim.
It showed "eval err" for that plot.
The expression of the internal node seems different from the normal output expression
The circuit is big and I will run the simulation with parameter sweep, so I want to set Output Save as "Select" to save hard disk space.
What should I do to plot the internal node signal in post-layout sim?
Thanks and regards,
Yutao
I do not have an ADE-XL license, I only have an ADE-L license.
I want to run monte-carlo simulation using spectre without ADE-XL license.
Also, I cannot use any simulator(such as hspice) other than Spectre.
I wonder if there is a solution.
virtuoso : IC6.1.6-64b.500.14
Spectre : 16.1.0.538.isr11
Hi all,
I successfully extracted the calibre view of my circuit and now I am creating the config view to perform post-layout simulations.
I created the config view using the spectre template and it generates the view list and the stop list required to simulate. However, when I change the type of view between schematic and calibre the simulation results obtained using ADEXL are the same. I probed adding "calibre" to the view list in the config but it did not work.
I am sure that my calibre is correctly extracted because when I simulate the calibre view using ADEL and changing the environment and adding calibre, the simulation result is different than schematic.
Does somebody have any idea about this problem?
Thanks in advance,
Rolando
I'm running 6.1.7, and I inadvertently ran a long corner sweep with "save all". I now have 600 corners with 500MB psfxl files each. I only use about 6 or 8 waveforms from each corner to create my output eexpressions. Resetting up and rerunning the test is infeasible. Is there a way I can save out those key outputs, and delete the rest from the psfxl file, so that I can still reference the data from maestro assember without maintaining 300GB of signals which are of no use to me?
i use Centos 7 x86_64
[root@soc02 ~]#cat /etc/redhat-release
CentOS Linux release 7.7.1908 (Core)
[root@soc02 ~]# source /cad/cadence/CIC/ic.cshrc
[root@soc02 ~]# virtuoso
WARNING: HOST <soc02> DOES NOT APPEAR TO BE A CADENCE SUPPORTED LINUX CONFIGURATION.
For More Info, Please Run '<cdsroot>/tools.lnx86/bin/checkSysConf' <productId>.
*ERROR* Display ":10.0" doesn't support 24-bit, 16-bit, or 15-bit true color needed to run this application. Please reconfigure Xserver with an appropriate visual.
[root@soc02 ~]#/usr/cad/cadence/IC/IC_06.17.709/tools.lnx86/bin/checkSysConf IC6.1.7
the log follow below,the 64bit package is ok is need install 32bit package ? because 32bit package looks like fail from log ?
or have any way to fix it thx.
WARNING: CheckSysConf detected your system is CentOS. This is not supported.
Only the following OS versions are supported by Cadence:
www.cadence.com/.../cadence-platform-support-plan.pdf
We will perform system verifications, but there is no guarantee Cadence software will run on this system.
=====================================================================
[Copyright 2002-2016] Cadence Design Systems, Inc. All rights reserved.
This program and online documentation may not be copied, modified,
re-published, uploaded, executed, or distributed in any way, in any
medium, whether in whole or in part, without prior written permission
from Cadence Design Systems, Inc.
=====================================================================
============== checkSysConf: Version 3.25 ====================
Operating System release details:
CentOS Linux release 7.7.1908 (Core)
Date information gathered: 銝 11??11 09:41:18 CST 2019
-------------------------------------------------------
Host Name ..............: soc02
Hostid .................: 758ca2a6
Operating System .......: Linux / x86_64
OS Version .............: CentOS Linux release 7.7.1908 (Core)
Kernel Version .........: 3.10.0-1062.4.1.el7.x86_64
Hardware Type ..........: x86_64
Memory .................: 15302 Megabyte
CPU model ..............: Intel(R) Xeon(R) Silver 4110 CPU @ 2.10GHz
No. of CPUs ............: 32
Total Swap Space........: 5119 Megabyte
X Server ...............:
Patch Data file ........: /usr/cad/cadence/IC/IC_06.17.709/share/patchData/Linux/x86_64/redhat/7.0WS/IC6.1.7
**************** Now verifying configuration ****************
Validating Kernel requirements...
Minimum Installed Status Info
-------------- -------------------------- ------ --------------------
3.10.0-123.8.1 3.10.0-1062.4.1.el7.x86_64 PASS
Validating MEMORY requirements MegaByte ...
Minimum Installed Status Info
------- --------- ------ --------------------
2048MB 15302MB PASS
Validating SWAP requirements in MegaByte ...
Minimum Installed Status Info
------- --------- ------ --------------------
4096MB 5119MB PASS
Validating DISPLAY requirements...
Minimum Installed Status Info
----------------- ---------------- ------ ----
8 planes PASS
PseudoColor TrueColor
Validating PACKAGE requirements.....23 to check
# PACKAGE Release Build Installed Arch Status Info
-- ------- ------- ----- ---------- ---- ------ --------------------
1 glibc 2.17 55.el7_0.1 2.17-292.el7 i686 PASS
-> 'GlibC'
2 glibc 2.17 55.el7_0.1 2.17-292.el7 x86_64 PASS
-> 'GlibC'
3 elfutils-libelf 0.158 3 - FAIL Package not installed.
-> ----------------------
-> 'Libelf Library'
4 elfutils-libelf 0.158 3 0.176-2.el7 x86_64 PASS
-> 'Libelf Library'
5 ksh 20120801 19 20120801-139.el7 x86_64 PASS
-> 'ksh'
6 redhat-lsb 4.1 27 - FAIL Package not installed.
-> ----------------------
-> 'lsb'
7 redhat-lsb 4.1 27 4.1-27.el7.centos.1 x86_64 PASS
-> 'lsb'
8 mesa-libGL 9.2.5 5.20131218 - FAIL Package not installed.
-> ----------------------
-> 'Mesa libGL Library'
9 mesa-libGL 9.2.5 5.20131218 18.3.4-5.el7 x86_64 PASS
-> 'Mesa libGL Library'
10 mesa-libGLU 9.0.0 4 - FAIL Package not installed.
-> ----------------------
-> 'Mesa libGLU Library'
11 mesa-libGLU 9.0.0 4 9.0.0-4.el7 x86_64 PASS
-> 'Mesa libGLU Library'
12 motif 2.3.4 7 - FAIL Package not installed.
-> ----------------------
-> 'openmotif'
13 motif 2.3.4 7 2.3.4-14.el7_5 x86_64 PASS
-> 'openmotif'
14 libXp 1.0.2 2.1 - FAIL Package not installed.
-> ----------------------
-> 'libXp'
15 libXp 1.0.2 2.1 1.0.2-2.1.el7 x86_64 PASS
-> 'libXp'
16 libpng 1.5.13 5 - FAIL Package not installed.
-> ----------------------
-> 'libpng'
17 libpng 1.5.13 5 1.5.13-7.el7_2 x86_64 PASS
-> 'libpng'
18 libjpeg-turbo 1.2.90 5 - FAIL Package not installed.
-> ----------------------
-> 'libjpeg'
19 libjpeg-turbo 1.2.90 5 1.2.90-8.el7 x86_64 PASS
-> 'libjpeg'
20 expat 2.1.0 8 - FAIL Package not installed.
-> ----------------------
-> 'libexpat.so.0'
21 expat 2.1.0 8 2.1.0-10.el7_3 x86_64 PASS
-> 'libexpat.so.0'
22 glibc-devel 2.17 55.el7_0.1 - FAIL Package not installed.
-> ----------------------
-> 'GlibC-devel'
23 glibc-devel 2.17 55.el7_0.1 2.17-292.el7 x86_64 PASS
-> 'GlibC-devel'
Validating FILE existence .....0 to check
Validating NOTFILE existence .....0 to check
Configuration checks failed on this workstation (soc02), status is: FAIL
WARNING: CentOS is not supported by Cadence software. The software might not work correctly
even if no other errors are found. For the list of supported OS versions visit:
www.cadence.com/.../cadence-platform-support-plan.pdf
This system does not have the correct packages to run IC6.1.7
Run checkSysConf IC6.1.7 -P <PACKAGE>
to find out which products require this package.
Exiting checkSysConf ... Good-bye
Output is saved as /tmp/checkSysConf.soc02-2019.11.11.09:41.15349.log