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Current annotation on the symbol

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I am using IC6.1.7 and want to annotate DC voltages and currents on the symbol itself. While generating the symbol, under "Symbol Generation Options" I tick Load/Save then select "analog" from the drop down menu. I also tick Edit Labels and select Label Choice = analog pin annotate and Label type = ILLabel. This adds a cdsTerm("XYZ") on all the pins and is capable of annotating voltages but not current. It annotates something like this: 300.76m, n/a. 

What setting would annotate current also? I am interested in seeing something like this: 300.76m, 12.876u. And I want it to be annotated from top to bottom of the hierarchy.  


Difference between dft and the Spectrum

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Dear Sir, 

I would like to ask you please what is the difference between the dft function from the calculator and the Spectrum tool provided by ADE, 

I want to simulate the THD and the SNR of my amplifier, which one is better to use, 

Some people claimed that Spectrum tool is not that accurate, I would say it is up to their setting, what is the best setting to increase the accuracy of the Spectrum tool to read the THD and the ENOB.

Thank you in advance

Best Regrds

Transient Noise Analyses in Cadence

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Dear Sir,

I would like to ask you please what is the difference between the normal transient analyses and the transient noise analyses ? , 

for me I presume that that even normal transient simulation can show the noise in my signal.

Can you please tell me about the setting of the Transient noise analyses

Thank you in advance

Stochastic-mismatch model in Verilog-A

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Hello cadence community,

I have a question about adding models when trying to set up an MC simulation. I will be clear enough in what i'm doing:

1| I have my Verilog-A model working with no problems in DC and transient simulations. I've understood that I can use the following line of code in Verilog-A to declare a parameter and then call it in an input file:

(*cds_inherited_parameter*)parameter real my_parameter = 0;

2| When I set up my simulation (by using ADE-L or ADE-XL) in "Model Libraries Setup" I add a model file "myfile.scs" where "my_parameter" declared in my Verilog-A model is called:

simulator lang=spectre
parameters my_parameter=0.5
statistics {
            mismatch{
                     vary my_parameter dist=unif N=0.5
                     }
            } 

3| Now, I've understood that "myfile.scs" notation is used for spectre. But I'm trying to use hspice so, I want to create a new file "myfile.sp" and add it to in "Model Libraries Setup" when doing a simulation. I want to call "my_parameter" (and do a process mismatch) which is in my verilog-A model but this time using hspice. How can I do it?

Best Regards,

Esteban

Alter statement usage for trimming (reelaborate card)

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Hi all!

I'm exploring the potentialities of alter statement and I found the re-elaborate option (boolean type), which basically re-elaborates the circuit and trigger the expression evaluation in the circuit. 

I want to create a netlist capable of trimming a reference circuit, using in the first part a simulation a DC sweep to calculate through a cross() function the respective trimming word, and then put it in subsequent simulations.

I have tried something like this with no success:

alter1 alter param=trim_val_par value=int(cross(i("R0:1" ?result "dc-dc") 1.8e-6  1 "rising" nil nil)) reelaborate=yes

How I could perform it? Alt

Thanks!

WHICH SkillAPI can perform (ADEL)config view -> File -> Save Cell Table Data

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I want to AUTO export all extract_view list from current working config view,

then use bash script to AUTO re-extract ALL post layout view for better efficient.

The question is after I perform "config view -> File -> Save Cell Table Data" at config view GUI menu

the CIW shows related function is "'hedSaveCellTableData_w9", but I cannot find any information of this key word in (skill tool) API finder

My qestion is :

WHICH SkillAPI can perform  (ADEL)config view -> File -> Save Cell Table Data

THX~

Virtuoso flatten verilog netlist generation question

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Hi,

Since some sw does not understand the bus type instance format, I would like to have a flattened Verilog netlist.

Is there an option to generate flattened verilog netlist?

(Current output)

buffer I0[1:0] ( .Z(net0_1_, net0_0_), .I(net1_1_, net1_0_));

(Desired format)

buffer I0_1_ ( .Z(net0_1_), .I(net1_1_));

buffer I0_0_ ( .Z(net0_0_), .I(net1_0_));

Regards,

Monte Carlo Simulations: Defining Standard Deviation, Mean, Number of Iterations and Number of Occurances as Outputs

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Hello,
I am using Virtuoso version IC6.1.7.
I run a Monte Carlo simulation, with let's say 100 iterations. Then I calculate a scalar output, let's say offset voltage, and get an histogram.
1) How can I define outputs that give the standard deviation and mean of a specific scalar oupout?
2) If I run multiple Monte Carlo simulations with a swept parameter (each 100 iterations), can I make a plot of standard deviations and means of each MC run (using the outputs of SD and mean from previous question)?
3) Is there a way to calculate the number of occurances within a window of the distribution? ex: I run a MC simulation to calcualte the offset of an amplifier, can I devine a scalar outout that calcualtes the occurances of offset between 1mV and 2mV?
4) How can I et the number of iterations of a Monte Carlo simulation as output?
Many thanks in advance for your explanations.
Best regards,
Can

nlSetPcellName for a resistor

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Hi Andrew:

I had lines below in a libInitCustomExit.il file

;; Adds a random number and time-stamp to the end of the mdoule name of subcircuits.
pcellNameTable = makeTable("PcellNameTable" nil)
procedure( nlSetPcellName( cv paramNames paramValues )
  let( ( tmpStr )
  if( pcellNameTable[cv]
    then
       sprintf(tmpStr "%s" pcellNameTable[cv])
    else
       sprintf(tmpStr "%s_pcell%d%d" cv->cellName random() stringToTime(getCurrentTime()))
       pcellNameTable[cv] = tmpStr
    )
  tmpStr
  )
) ; procedure ** nlSetPcellName **

Here are the netlist it generated from a resistor.

subckt ppolyf_u_pcell1575840381553782469 PLUS MINUS B
parameters segL=2u segW=2u
    R0 (PLUS MINUS B) ppolyf_u l=segL w=segW
ends ppolyf_u_pcell1575840381553782469
// End of subcircuit definition.

R2 (net03 net02 net01) ppolyf_u_pcell890174431553784620 m=1 segL=2u   segW=2u
        
As you can see: ppolyf_u_pcell890174431553784620 and ppolyf_u_pcell1575840381553782469
are not the same.It will report an error in spectre simulation.

I want to change the code, then it does not add random number but a fix number.
For eg:
R2 (net03 net02 net01) ppolyf_u_pcell_0 m=1 segL=2u segW=2u
        
Then I can ignore

subckt ppolyf_u_pcell1575840381553782469 PLUS MINUS B
parameters segL=2u segW=2u
    R0 (PLUS MINUS B) ppolyf_u l=segL w=segW
ends ppolyf_u_pcell1575840381553782469

and include a definition:

subckt ppolyf_u_pcell_0 PLUS MINUS B
parameters segL=2u segW=2u
    R0 (PLUS MINUS B) ppolyf_u l=segL w=segW
ends ppolyf_u_pcell1575840381553782469
// End of subcircuit definition.

So there will be no error when I run spectre.

How can I change the skill code ?

CDL syntax error

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Ive created a Pcell that instantiates a PDK resistor and added a well tap.  I can netlist using 

ansCdlHnlPrintInst 


.SUBCKT resTest minus nwell plus 
*.PININFO minus:I nwell:I plus:I 
RR0 rpodwo R=655 M=1 $PINS MINUS=plus BULK=nwell PLUS=minus 
.ENDS 

However, calibre aborts with a syntax error, anyone know why? 

deepprobe to a bussed net in AMS

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Hi,

I'm trying to use a deepprobe instance from analogLib to probe a bused net inside one of the circuits in an AMS simulation. I found some rather old posts on this issue (deepprobe with AMS) and documentation on deepprobe when it was added to the analogLib not too long ago.

Since I couldn't make it work in my rather complex and large circuit, I set up a simple circuit to test what I was doing.

I created a test circuit with a bused net inside of it named Vint<4:0>.

Then I tried to reach Vint<2> from the test bench where the test circuit was instanced as I0.

If I do a spectre simulation, the deepprobe argument should be: I0.Vint\<2\> and it works perfectly.

In AMS simulation, buses in the netlist are noted with square brackets: 

wire [4:0] Vint;

Therefore, as this post suggest the deepprobe argument should be I0.Vint\[2\].

However, the resulting AMS netlist has this:

iprobe IPRB0 (I0.\Vint[2] , Vprobed);

which doesn't work due to the \ in front of Vint, which was added out of nowhere by the netlister. If I manually remove the \ from the netlist, it works!

It is worth noting that I tried using <> with or without \ and it doesn't work either (as expected) in AMS. I have also tried other combinations with no luck.

Am I doing something wrong? 

By the way, I'm running everything from ADE, using UNL netlister for AMS sims, and these are the tools version I'm using:

  • virtuoso IC6.1.7-64b.500.20 
  • ncsim(64)15.20-s005
  • spectre 17.1.0.307.isr6

Thanks!

-P

How to rename copy library with prefix/suffix added in all the cells

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Hello, 

I saw some of the posts regarding this issue. But, most of them are dormant for some time and I have some unique requirements:

1. The code should allow me to replace existing prefix with the new one

2. The code should add/replace prefix for all the cells hierarchically during the copy process. Eg. I copy A0_topCellA which has subcells names subCellA, subCellB; it should be able to rename everything as B0_topcellA, B0_subCellA,B0_subCellB.

3. It will only replace a specific prefix, if there is no prefix, it will add the new prefix. (Eg. #2)

Please let me know if there a short cut to do this embedded in Cadence system. If not, I highly appreciate any SKILL code in this regard.

Regards,

Kalyan

How to measure deterministic jitter from eye-diagram by using command

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Dear All,

I want to measure deterministic jitter from eye-diagram by using command.

Manually, using cursors one can measure the  deterministic jitter (DJ) manually. But for doing this across corner is very much time consuming and error prone.

Can anybody please tell how to measure deterministic jitter from eye-diagram by using command which can be used in ADE-XL across corners.

Kind Regards,

Issues with using abEyeCross.il (giving WRONG results when compared to EYE-Diagram)

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Dear All,

 I am using abEyeCross.il from solution 11395772(https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nX0ZEAU&pageName=ArticleContent).

This is to find peak-to-peak Deterministic jitter (DJ) when I give a supply sinusoidal noise ( of 20 mV amplitude and 11.11 MHz frequency).

I am giving a PRBS pattern of UI=31.25 pS as the input data stream. I am now finding the DJ in the output data stream.

I am trying to verify that whether  abEyeCross.il is giving correct result when I compare manually the Deterministic jitter from the actual Eye-Diagram.

But, Looks like I am getting wrong result from abEyeCross.il.

Can anybody please tell why it is giving wrong results. I am also posting the both way results below.

 abEyeCross.il Results:-

I use the commands in CIW as below:-

jit=abEyeCross(vtime('tran "/rxleq_lpbk") 0n 105n 31.25p 0 "rising")
srrWave:0x33bed0a0
DJ=peakToPeak(jit)


DJ=3.123789e-11 =31 pS



I got DJ = 31 pS

Below shows the DJ value I got from Eye-Diagram:-

Modelfile not loaded in ADE

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I transferred an existing project with PDK into our environment.

In .cdsinit it is set:

  envSetVal("spectre.envOpts" "modelFiles" 'string "/model_libraries/models/lvt_mos.scs;TT")

When verifying in the CIW via

 envGetVal("spectre.envOpts" "modelFiles")

I see it is set properly.

But when opening ADE and creating a netlist, it does not include this modelfile. It also does not show the modelfile in the ADE modelfile-popup-windows - its just empty.

This not only for existing cells, it is also for newly created cells.

WhenI select the modelfile in the ADE modelfile-popup-window, it is included in the netlist.

How can I make it to include the modelfile ?

What does prevent the modelfiles to be loaded ?


How do I parameterize analoglib.ipwlf's cdf parameter"PWL file name"

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The situation is different PWL file for  different corner

I want to  parameterize analoglib.ipwlf's cdf parameter by fill "FILEPATH"/VAR("FILEPATH")/VAR(FILEPATH)

then I set variable combine with corner setting

But now all the phrase above does not work

The CIW log is Uable to open waveform file '"FILEPATH'

Backwards Time Simulation to Determine Boundaries of Convergence

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Is it possible to run a backwards time simulation in Virtuoso 6.1.7?

I am trying to find out how far from an equilibrium I can set the initial conditions of a circuit's nodes and still have them converge to that equilibrium.  After the simulator solves a set of differential equations for a set of initial values, I want to trace the path of the points as they move backwards in time so that they diverge from the equilibrium instead of converging.  Is there a way I can set up ADE or another simulator get this data?

To be clear, I don't want to simulate what happened in the circuit's past while it was operating in a steady state.  I'm looking for conditions that may cause a circuit to have start-up issues.

how to short circuit in layout for analogLib\iPRB kind behavioural cell

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hello experts,

I noticed from other post that lxRemoveDevice  which can remove devices and short in the process. but that's some script to process while netlisting. can we set some property in the symbol like "nlAction" = ignore as basic/noConn. is there similar user property we can set to get remove the current cell and short the terminals when layout/lvs/drc, etc?

thanks,

David

Updating a PDK technology layermap and technology

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Hi.

We're trying to update one of our PDKs at lab to contain the latest Layout Editor information.

We received from the vendor a .map file and a .tf file, and I would like to verify that we are updating them properly.

1. To my best understanding there is no such a thing as "map file" update, just use the new layermap for stream purposes. Is that correct?

2. Updating the technology file looks more cumbersome. Using the "Technology File Manager", there is a way to merge technology files. To update our process, should we use this procedure? If not, what is the proper way to update a technology file?

Thanks again,

Matan

Standard Cell Library Integration

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Hi, 

   New to Cadence tools and I am not sure how to integrate a PDK standard cell library into Virtuoso for schematic design and layout. I have the libraries imported and can view the symbol and schematic. I am using a IBM 0.18 PDK but the standard cells are broken into cdslib (Schematic and Symbol) and another directory tree with LEF, GDS, netlist, and Verilog files.  

I can not figure out how to link the libraries consisting of symbol and schematic views with the layout and additional views. 

I need some help here. 

Thanks!

Drake

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