Hi, I am trying to check the DRC for my layout design, when I run DRC I got this error with the following message:
sh: -c: line 0: syntax error near unexpected token `('
sh: -c: line 0: `cp /tmp/CDS_ENVF77zvv /{Path}/.cdsenv'
Also, I can't find the file ".cdsenv" in the provided path.?!
Thanks in advance!
Hi,
I am using SKILL code to do netlist generation outside of the ADE gui. I do the following:
envSetVal( "spectre.envOpts" "setTopLevelAsSubckt" `boolean t)
envSetVal( "spectre.envOpts" "switchViewList" 'string "spectre cmos_sch cmos.sch schematic veriloga symbol")
envSetVal( "spectre.envOpts" "stopViewList" 'string "spectre symbol")
design(theForm~>myLibField~>value theForm~>myCellField~>value theForm~>myViewField~>value)
createNetlist(?recreateAll nil)
After execution the ADE Assembler license is still checked out. I know of 2 ways to "check in" the license.
1) Open the ADE assembler gui and close it.
2) In the License manager set the idle time to a small number.
I would prefer to just "check in" the license after the createNetlist call is done. Is this possible?
Thank you,
Brian
P.S. - I am using cadence version ICADV 12.3-64b.8
Hi,
I am running Cadence version ICADV 12.3-64b.8
When I open multiple db’s based on similar testbench (Example: same I/O, Stim etc. but use netlists with different sized devices) and plot a signal from all the db’s, I see them plotted with same signal name on top of each other but there is no way to determine which wave corresponds to which db.
Is there a display setting that will show this detail for the signals in the waveform viewer?
One solution might be to identify signals as you plot them, but this will not work when I search across db’s for a signal name and then plot it across db’s.
Thanks
Dave
Dear all.
Today, when I run my file in Virtuoso, the dialog appeared:
(icLic-23) License Virtuoso_Layout_Suite_L ("95300") is not available to run Layout-L. Would you like to try checking out the License Virtuoso_Layout_Suite_XL ("95310") instead?
Normally, I choose Yes, but I made a mistake and chose Never. As a result, I never open any file anytime.
Could you please tell me how to fix this ? I really appreciate your help.
Thank you,
Nguyen N
Hi,
Is it possible to probe internal nodes for a stacked Schematic pCell.
I have a stack config where multiple transistors are stacked and want to probe internal node.
When I try this through normal method it does not seem to work.
1. in the ADE XL window -> Outputs -> To BE Saved -> select on Design.
2. Then I select the internal node
But this does not add the signal in the Outputs subwindow in the ADE XL Editor.
I tried to check the netlist but it doesnot show there also.
Thanks,
Mihir
I am going to buy a new PC for running Cadence Virtuoso. The simulations that I will be working with would be DC, AC, PSS, Noise, and Transient (Specifically because I might need to run these in ADEXL to have Monte Carlo outcomes). The Cadence version I am currently using is IC6.1.6-64b.500.6.
Evidently, the higher spec, the better! However, I am trying to understand which part should I invest more, given the fact that I like to have parallel processing to maximize the speed. I was wondering if I should have more # CPU cores and less RAM or vice versa. I would like to thank you for your valuable comments!
Hi,
Is it possible to run aging simulation for two pattern, say we we want to run aging sim for 10 years, for first 5 years VDD=1.8V & temp=30 and next 5 years it should be VDD=3V and temp=45.
I explored "rxprofile" options but couldn't found a way to do it.
Thanks,
Nasser
Hi,
I have a couple of questions regarding how Voltus-FI static IR-drop analysis:
1. How does it treat decoupling caps and dummy or inactive transistors (Pmos with VDD-connected gates, Nmos with grounded gates, etc) in the design? Would it regard it as ideal open circuits with 0A current going through them, or not?
2. In IR-drop power rail analysis, we are aware that users can specify static current values for nets in the static current input file, but is there a way to specify the *ratio* of currents branching into 2 or more blocks devices?
In the Voltus-FI user manual, there is a description of the Average Static Current Analysis using the switching activity information of signal nets, and Net based average power to specify different power values for different nets. If this is the approach to take, can this method be configured through ADE Assembler GUI?
Thanks,
Henry
Hi,
I need ful hierarchy for all the fet in the design. A flat netlist is the easiest way to go but spectre does not has a way to get any flat netlist. So the only option is to get it from some SKILL code. Does anyone has a handy skill code that give all the hirarchy listing for all the fets .
Hi,
When I have a s-parameter file in the circuit, PSS will report error and suggest to use hb engine. I wonder if there is a way to include s-parameter file and keep shooting engine in pss.
It says I can use rational for interp, but the simulation still fails.
Thanks!
Hi all,
I am searching an option to export only netlist for layout in icfb.
Somebody please help me.
Thanks,
Ganesh Doddipatla.
HI ,
Does anyone know how to check our env to see if we have Voltus license?
thanks
Nhumai
Hi,
I have another question on PSS simulator with hb engine.
I am simulating a circuit that settles after a certain time. If the circuit does not settle properly, for instance, ends up with an unwanted oscillation, then I expect the simulator to complain and will not converge.
In that case, if I use PSS with shooting engine and choose a certain tstab time, then PSS simulator fails to converge and will report simulation error and will not generate output data.
However, if I use PSS with hb engine and choose the same tstab time. simulation runs and gives a warning after it reaches the specified max. number of iterations, saying that it did not converge and the result may not be accurate. However, it still calculates the outputs data based on the last iteration results, which can be misleading, if I just look at the output data and not check the log file.
Is there a way to let the simulator stop when it did not reach convergence, showing sim error in the output fields, instead of showing inaccurate data?
I am using IC123_isr10 with mmsim151. I am not sure if this is related to just PSS with hb engine, or related to some generate spectre settings. Maybe this is just something specific to me, but I'd like to ask here to see if there is something can be done.
Thanks!
Hi All,
I have big Analog, small digital block. Most of my design is custom based Analog, done with Virtuoso Schematic and Layout. the small digital blocks, i did digital flow, exported gds and verilog netlist, converted it into CDL for LVS comparison.
When I tried to run LVS from Virtuoso using PVS , the first time it failed(Missing NMOS and PMOS) So I had added N-Well surrounding the instance (excluding NMOS), and this time the LVS is clean.
But the problem re-occurs when i instantiate this module in new cell, and try to run LVS from that hierarchy. I tried flat LVS run as well. Still same error. My tool details as fllows.
Digital flow: Genus 16.10, Innovus 16.1
Virtuoso: 6.17, PVS 15.22
My digital cells Deep-N-Well and i have only single power domain.
Do anyone have any rough idea on where should i debug? if need any details, let me know. I will try my level best to put as much as possible
Thanks!
Aarthy
hi i'm trying to apply lvs test to the layout of my circuit that is a transimpedance amplifier which uses 4 spiral inductors .the problem is when i try to check lvs it gives me the following errors :
no matching ".SUBCKT" statement for "SPIRAL_STD"
source can not be read
what should i do to solve this ?
thanks in advance.
Hi,
While placing Auto via from M4(H) to M6(H) and there are some M5(V) routing on them it will add via where M5 is not there and will keep spacing between M5s those are routing and M5 in via.
It is keeping 0.55 where it can keep less space like even 0.1.
The tool is keeping more space than required. Where can I change the space so that I will get more vias.
Thanks,
Ganesh Doddipatla.
Dear Community,
I wonder if I can set the S-parameter data file path parameter in the schematic as variable and sweep it among discrete values.
Sample scenario: Some data link has an input power dependent characteristics which are modelled 1mm.s3p 2mm.s3p 3mm.s3p, which corresponds to 15 12 and 9 dBm of input power.
I want to do a parametric sweep grouping this two parameters. Anyway, cadence does not accept file path as a variable.
Could you please help me with that?
Best Regards,
Armen
Doing noise simulations, it seems that I can only select one single node to plot the resulting noise voltage.
Selecting multiple nodes seem not to be provided - right ?
I want to plot the noise voltage for more than one node, e.g. I have a multistage analog circuit and want to plot the noise voltage densities at the interstage nodes - how can I do that ?
Hello,
I am running a mixed signal simulation where my standard cell instances are defined using a .cdl model file which contains information like this.
.subckt adc12_stdcell_ADDFHX4 CO S A B CI
M0 net76 net82 VSS VSS n18 l=0.18 w=0.96
M1 VDD net82 net76 VDD p18 l=0.18 w=1.44
M2 CO net119 VSS VSS n18 l=0.18 w=2.4
.............
M27 net131 net84 net138 VSS n18 l=0.18 w=1.52
M28 net137 B net138 VSS n18 l=0.18 w=1.36
M29 net137 net84 net88 VSS n18 l=0.18 w=1.52
M30 net138 A VSS VSS n18 l=0.19 w=1.41
M31 VDD A net138 VDD p18 l=0.18 w=2.1
.ends ADDFHX4
*.SCALE meter
.GLOBAL VDD VSS
The gates are just symbol views in Virtuoso. The model file is selected under the Hierarchy Editor using the Set Cell View --> Specify SPICE Source file to pick up the .cdl file.
So far I haven't been able to get AMS to recognise the .GLOBAL statements and so my VDD and VSS nets within the CDL standard cells are unconnected.
I've searched around on the Community but haven't hit the information I need.
Can anyone give me a few pointers?
Many thanks,
Matthew Cordrey-Gale