Hi,
I have a design with standard cell. For the standard cells I only have layout and symbol. When I try the ADE XL netlister, it could not descend into these standard cell since there is no schematic for them. If I put the symbol in the switch and stop view lists , it does not show the standard cell interface.
Satendra
Hi,
I am Bindu. I am a beginner in cadence. please suggest the tools required to design memristor crossbar architecture in cadence. And how to purchase them thier system configurations etc.
Please help me with this issue.
Thanks in advance.
With regards,
Bindu
Hi All
I am trying out to use amsd block to configure some cells to be bound to a spice netlist.
inside the amscf.scs file, I am writing some thing like:
include "analog_top.scs" //hierarchical netlist for whole analog design
include "modelfile.scs" section=tt //model files and section selection
include "analogControl.scs" //simulator and analysis settings
amsd{
portmap subckt=ana_top porttype=name autobus=yes
config cell=ana_top use=spice
ie vsup=1.5
}
My intentions is to use the schematic for whole analog top in the DUT.
Unfortunately, the end results is not good.
The ana_top cell has been resolved to "worklib.ana_top:spice-skeleton" as shown in the log file, with "-libverbose" option in irun.
But such "spice-skeleton" view contains no real content, just bunch of parameters.
And according to the simulation results/speed, it shows that the ana_top cell is indeed empty.
Does someone have clue about where may go wrong?
Best Regards
Yi
Hi,
I do not understand how I can run the examples provided by cadence in the path ./tools/dfII/samples/artist.
Especially I am interested in the pllMMLib testbenches.
I already found a tutorial on "Noise aware design flow" - but the mentioned wizards are not available.
I am using ic6.1.7.500.1400.
What I would expect from an example testbench is a functional ADE state saved with the testbench, which just can be started right away.
But this is missing and it seems to be a real pain to get this examples running.
As an experienced Agilent ADS user I am really disappointed that I am struggling that much in Cadence to run a simple example.
How can I run the examples ?
And where do I find a straight forward tutorial ?
Thanks !
Is QRC Template file (QRC .rcx_setup.tpl) created by QRC run or this file is a part of a PDK and QRC use it for the run?
HI,
I have a large layout and I need to see for example the net name A all the way from M5 to M1. However, when I use connectivity->net->mark the tool highline every thing include any nets which are not connected to net A.
how can I set the Marknet options form to highline only net A. I want to see if net A connected correctly.
thanks
Nhumai
Hello,
Before running my transient simulations, I want to change the multiplicity factor of some blocks. ( I am using spectre / spectreXps )
I use the command lines below. Does the simulator change the multiplicity of each block, then run the simulations. Or, it takes only the first (or last) line ? If it is the case what should I write to make the simulator make all changes at once then run. ?
Thanks,
Kotb
Loadmimic0 alter sub=X8SEG\<0\>.XSEG\<7\> param=m value=4
Loadmimic1 alter sub=X8SEG\<0\>.XSEG\<0\> param=m value=2
Loadmimic2 alter sub=X8SEG\<1\>.XSEG\<7\> param=m value=6
Loadmimic3 alter sub=X8SEG\<1\>.XSEG\<0\> param=m value=8
tran tran stop=1000n step=100p
Hi,
I want to know what is the procedure that I have to follow in order to generate an SDF file from a custom digital layout I made using Virtuoso.
I have the Verilog of the standard cells I used (Clock Buffers, Inverters, etc.) and the .lib for each of the cells. I have also generated the netlist of my digital design from my schematic, using Ncverilog.
Which are the next steps I need to follow?
Thank you in advance for your valuable help!
Kind regards,
anm
HI All,
I have a data base in icfb 5.1.0 and we want to convert it to virtuoso version 6.1.6-64b.
First we convert the schematics and symbols from icfb 5.1.0 to virtuoso 6.1.6-64b then we want to run lvs using that conversion schematics in virtuoso 6.1.6-64b against icfb 5.1.0 layout to make sure that we didn't make mistake when we converted schematics and symbols. Is that any way to do that ?
thanks
Nhumai
Hello Everyone,
I am using Cadence Virtuoso through a server (using Putty and Xming), on a Windows 10 laptop.
Everything was working fine and suddenly when I tried to open the Calculator, the windows is frozen, (i.e. the Calculator windows shows up, however when I click on it, it just disappear).
I tried everything I know to get around it (reboot Virtuoso, using another laptop, etc) but it did not work out.
Do you guys have any idea?
Thanks,
Hi
I created an inverter with pmos and nmos and declared their widths as variables (Wp, Wn) by keeping the lengths constant. Now I want to plot VOUT vs VIN for different values of Wp/Wn ratio instead of doing parametric for Wp and Wn separately. I mean there is any way for directly sweeping the equation formed by variables.
I want to plot gm (y-axis) vs id (x-axis) for a transistor. Google search shows me how to plot gm/id vs vgs or gm vs vgs but not the gm vs id, i. e., the value of gm sweeping id. Can anyone help me to plot this? My testbench and the ADE analyses are given below:
Hi everyone,
I have a circuit include 1 cmos and 1 resistor. I want to measure power consumption on each device.
Can you help me how to measure it?
Thank you. Have a nice day.
hello experts,
this is just for testing bench purpose, how can I use signals across hirarchy w/o I/O ports, e.g., I want to see BlockA/BlockSub/signalB somewhere else?
thanks,
David
Hi Team,
I am using IC 617 for transient simulation. After the simulation, I can plot the output waveform. However, my desired form of output would be in a table format.Moreover, for instance, I want it to output from 1000 ns and record the value every 1 ns. (this was not the simulation steps size)
Currently, I am using "right click--send to--export" Then I fill in the blank of "start" to be 1000nS and "step size" to be 1ns.
However, is there a better way to directly show the table in cadence visualization window? like :"right click--send to--calculator/table":'
I tried "sent to--table" but I don't know how to choose the start and the step of the generated table.
Thanks
Allen
Hi,
I have a simulation for generating MOS transistor data using a 4 nested sweeps (VGS, L, VDS, VSB) for a 4-terminal NMOS device. I am able to setup the simulation and run it with all working OK. However, I am trying to get the results into a .csv or .dat file in a clean manner.
I am using IC617 with Spectre version 16.1.0.479.isr9.
I know this question was asked before over here https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/33105/parametric-analysis but the solution to use MATLAB is not something I can do at the current time. I will have to stick with using OCEAN or using a manual click and save as .csv
My setup is such that the VGS sweep is configured in ADE XL analysis window and the other sweeps are configured within the parametric analysis window (from top to bottom VSB,VDS,l)
My initial way to print the data into a .csv file was to use ocnPrint() which I know works best for plotting waveform data:
selectResult('dc)selectResult('dc)ocnPrint(?output "~/MOS_sweep/gm.csv" ?numberNotation 'scientific getData("M0:gm"))
This results in a .csv file that is a little cumbersome to read in MATLAB, in that it has blocks of 2-D data (with VGS and l as the sweep variables) and then multiple such blocks for swept values of VDS and VSB.
By right clicking the parameter under the 'dc folder in Results Browser and creating a table, however the data is listed a 2-D data which is much more convenient to me. My question is how to invoke the table and save that as a .csv file from OCEAN?
AG
I'm using Virtuoso 617. I am trying Route->Power Routing feature . The Power Routing Options GUI form (with Block Ring tap
is choosen ) is pre-defined with "Horizontal Routing Layer" = "M1 M3 M5 M7" and "Vertical Routing Layer" = "M2 M4 M6 M8".
I want to do the opposite. How can I change this ??
Thanks ....
I'm using ADE Assembler (IC6.1.7-64b.500.17).
I have a parameterized desgin variable. I have an expression for the noise and for a certain current. The noise and currents are both calculated/evaluated correctly for the swept design variable and show up in the results.
When I use the calculator and use the waveVsWave to plot the noise vs current, I get the plot that I'm after.
However, when I add that expression from the calculator to the ADE outputs, assembler tries to evaluate that expression for each single design variable value when a simulation is performed.
Resulting in an 'eval err' in the output (because it tries to plot a single point) and not yielding the wanted (noise vs current) plot after the simulation is finished.
How can I evaluate/plot an expression only when all the simulations (for the set of design variables) are finished?
Emiel
Hi there!
I am trying to run ams simulation for a big design mixed of digital and analog. However, the output of simulation for the digial block is always tied to zero and basically there is no output.
Can anyone help me out through this problem? (The following is briefly explaining the steps done)
Cadence Virtuoso: 6.1.7 -- INCISIV 15.2 (irun 15.2)
Digital part of the design is a verilog netlists generated from synthesis tool (generated netlists using both Cadence Genus and Synopsys Design-vision).
it means inside the netlists all behavioral modules have been already translated and mapped to technology components.
These steps have been all done:
This is an example of the imported netlist: (I changed the real component names to StandardCell_#)
// Created by ihdl
module xorGate_synopsys ( rst, clk, a, b, y );
input rst, clk, a, b;
output y;
wire n1, n2, n3, n4;
StandardCell_1 U2 ( .A(rst), .Z(n1) );
StandardCell_2 regxP_reg ( .D(n4), .CP(clk), .RN(n1), .Q(y) );
StandardCell_3 U6 ( .A(b), .B(n3), .C(a), .D(n2), .Z(n4) );
StandardCell_4 U7 ( .A(a), .Z(n3) );
StandardCell_5 U8 ( .A(y), .Z(n2) );
endmodule
Hi,
I am simulating hundreds of corners for more than 10 tests on ADE-XL and I need to optimize the use of licenses as much as possible.
When running tests sequentially in series, all my licenses are taken from the first test in the stack and I have to wait to the test to finish so I the next one can run.
I try solving this running simulations in parallel.
Is there any other method available, as this will reduce the time each simulation takes to run ?
As I launch these simulations during night, launching them in series is not an option, since if one of them gets stuck all the others will never start and I will arrive in the morning and see that all the simulations didn't even start.
Is there any method which allows me to launch simulations in series, but one gets stuck during a t amount of time, the simulation is automatically canceled ?
Thanks in advance.
Best regards,
Pedro