Dear all,

Calculator function firstVal() returns the first x-value of a waveform.

I wonder, if there is something like firstVal() to return the first y-value.

Example:

Imagine a DC voltage sweep from 1 V to 2 V and a resulting output waveform VS("/result") with some arbitrary data.

firstVal(VS("/result"))

returns 1.0, as my voltage sweep starts at 1.0 V.

Of course, I could find the corresponding "first" y-value with

value(VS("/result") firstVal(VS("/result")))

The point is though, I need this in a way more complex function, and the formula gets very complex and hard to read if there was no simple and compact way, like a hypthetical "firstY()" function to do the job, like this:

firstY(VS("/result"))

Obviously, ymin or ymax cannot do the job, as the data is arbitrary, i.e. not in ascending or descending order.

Dear all,

I wrote a very simple custom calculator function with the following function signature:

procedure( countSamples( signal )

 <code>

) ; countSamples

I also added - in the same SKILL file - the following GUI builder information

;;;;;;;;;;;;;;;;;;;;;;;;;; GUI builder information ;;;;;;;;;;;;;;;;;;;;;;;;;;;
ocnmRegGUIBuilder(
 '(nil
  function countSamples
  name countSamples
  description "Count the number of samples avaliable for the given signal."
  category ("Custom Functions")
  analysis (nil
      general (nil
        args ( signal )
          signals (nil
                signal (nil
                      prompt "Signal"
                      tooltip "The signal vector to count the number of samples for."
                      )
           )
        inputrange t
      )
  )
  outputs(result)
 )
)

This is pretty much like the example provided in the Cadence Help.

However, it acts a bit weird. If I click on it in Calculator, with no signal already selected in the buffer, nothing happens. With signal already in the buffer, it nicely wraps around it (e.g. countSamples(VT("/result")) ).

There are other calculator functions like Kf() as an example, which also just have one mandatory argument. When I click on it - again with an empty buffer - it adds "Kf()" to the buffer, such that I can then enter the argument in the brackets. This is a more intuitive behaviour: action by the user like a click on the function follows action in the Calculator window.

What am I doing wrong, that my function does not behave like this as well?

In post-layout simulation, there are an array of net voltages being saved in result browser. For example,

• net_name[1]
• net_name[1]:1
• net_name[1]:2
• ....
• net_name[2]
• net_name[2]:1
• ...
• Other nets...

Those net with ":" are sub-net found in layout.

Goal:

1. Filter out net_name[1]
   1. Problem faced: Square bracket could not be recognized in the shell search. No matches at all.
   2. Solution Tried: Tried to use *"net_name["* but still no match.
2. Only show net's voltage without ":"
   1. Problem faced: Found negate syntax for shell pattern matching but could not tried it out. 
   2. Solution Tried: net_name*[^:]* but no correct match
3. Filter out net_name[1] and without ":"

Can someone help me point out the correct syntax? RegExp solution is acceptable too. Thanks as it will help me work more efficent in work!

Dear all,

does anyone know where the code of a Custom Calculator Function gets stored when I load a SKILL file as a custom calculator function using the "fx" button in Calculator?

The problem is, that one can mess up Cadence ADE and the Calculator so badly, that it crahes (or rather freezes up) permanently, i.e. even after re-starting Virtuoso and then invoking Calculator again.

It must be somehere in the user's project home, because when restoring the whole home directoty to the state it was before, Calculator can be started again without freezing up.

However, a manual inspection does not point me to what file may cause the trouble.

Edit 1:

There is a comment by Andrew Becket in another post, that says: "When you use the "fx" button it actually adds it into your home directory's .cadence dir, not the working directory, so it should be visible across multiple workspaces for then same user."

community.cadence.com/.../automatic-load-user-defined-calculator-functions

Edit 2:

Andrew is right. It's in the HOME not project home.

HOME/.cadence/dfII/viva

In there, there is a file cusomFunctions.ini, and in this file, I can see the path to the SKILL file.

However, I don't understand then why restoring the project home directory solved the problem of a freezing calculator...

---

Apparently, the freezing up can be achieved by using string escape characters in the tooltip of a parameter in the ocnmRegGUIBuilder section, like

tooltip "Edge type 1. Either \"rising\" or \"falling\""

Hi all, for a particular test bench, usually before running a sim, I will have a standard operating procedure of

One time only

1. Checking the High Performance Simulation Settings (The accuracy settings)

2. Checking Job Policy (which is available in Run Preview currently, but I am using command mode, and it's not showing enough info)

Regular

1. Checking the simulation files (which DSPF files I am using)

2. Check particular Design Variables that I am interested (I actually hoping to have comment/note of all these design variables and their default value)

3. Corners selected (which is available in Run Preview currently)

Is it possible to make a new dashboard for review these stuff in a glance using SKILL or customise the Run Preview Tab? Hope to have some pointer for relevant API. If I successfully make it, will share around here if people found useful

(I understand that this is a big stuff, feel free to break down and if it's possible to achieve one of it, you can share the relevant function with me)

I've written a custom function in C++ that I need to compile using mmsim_genplugin. Is there detailed documentation on mmsim_genplugin? My searches haven't yielded results. 

Specifically, I'd like to know:

1) My function has one library dependency (armadillo), how do I include it? I can compile in gcc as follows:

g++ myfunction.cpp -std=c++17 -I <path_to_include_folder> -O3 -L <path_to_libraries_if_needed> -larmadillo -lopenblas

2) My function makes use of C++ features up to C++ 17. How can I confirm if mmsim_genplugin supports C++17?

Hi,

My virtuoso version is: ICADVM20.1-64b.CUSTISR33.26

I'm running a transient simulation using Spectre X and I get the following message regarding DC convergence:

"Notice from spectre during IC analysis, during transient analysis `tran'.

GminDC = 1 pS is large enough to noticeably affect the DC solution.

dV(MNW.RF.clk_pdet_int) = -34.2307 mV

Use the `gmin_check' option to eliminate or expand this report.

Bad pivoting is found during DC analysis. Option dc_pivot_check=yes is recommended for possible improvement of convergence."

I get the same message in the DC simulation. I tried to add the dc_pivot_check=yes option in the additional parameters of the MISC section and I got the same message above with the following warning saying the dc_pivot_check that I set is ignored.

"Warning from spectre during hierarchy flattening.

WARNING (SFE-106): "input.scs" 79: Parameter `dc_pivot_check', specified for analysis `tran', has been ignored because it is an invalid analysis parameter. Specify a valid analysis parameter and rerun the simulation. Type `spectre -h tran' to get more information on valid tran analysis parameters."

Can you please help me understand what did I do wrong and how can I successfully specify dc_pivot_check=yes? Any other suggestions to help with this bad pivoting issue?

Hello,

I was running transient simulation on a large circuit in ADE Explorer,and it took 4 days to complete. However, it returned "eval errr" for the output expression. In my previous experience, it's likely due to an invalid expression so I'm working on fixing it. But I really don't want to spend another 4 days to run it, and even worse, that gives me another "eval err" at the end. Is it possible to update and re-evaluate an expression that returned "eval err" without re-running the simulation?

An additional question, the log of the transient simulation has these lines. Does that mean spectre had a convergence issue with homotopy = gmin? If I have to re-run the simulation, how can I let spectre to skip the first one and use homotopy = source directly? That'll likely save me 40% of the simulation time.

 xdspf file syntax is checked with spefchecker but file created with calibre-pex is giving the segmentation problem. Is there any way to check this?

Hello,

I am trying to perform local optimization in Cadence Virtuoso 6.1.7 ADE Assembler. However, I am encountering an error as shown in the picture. What steps should I take to resolve this?

I have watched some videos on the internet where they mention a "set starting point" option, which seems to be missing in this version. How should I proceed? Could you please explain the steps required to achieve this? Thank you.

I would like to Ignore dummies when performing LVS using PVS.

I'm using the virtual foundry GPDK 45nm (Cadence) to do some research.

I note in this post:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/58057/cdsenv-setting-with-backannotation-in-layoutxl/1393995#1393995

BrendaGray suggests:

lvsIgnore: When set to "true" or checked, it indicates that the dummy should be ignored during LVS checks.

This would do but I'm not sure where to place it within the PVS submission form:

I tried putting it in the Filter options shown above but it is complained and should it be lvsIgnore=TRUE wherever it's put?

I do know that a lot of designers recommend simply updating the schematic but as this is a 'virtual foundry' I see no harm -  in Calibre the option exist.

Hi ,

Hope you are doing well,

I need help importing the.csv file to my ade.xl.

I am facing a problem importing the csv file in the design variable, and i have attached screenshots of the errors that occurred while importing. 

Can you please help me solve this asap.

Thank you,

Kind regards,

Likitha BR

030768619

Hi all,

Is there any way to change switching activity and report power in Genus ,using Joules power engine .for example command similar to set_default_switching_activity in INNOVUS

Hi guys, I'm going to running my post-simulation with parasitic extracted, and the netlist of my device has been generated as "cell.pex.netlist", the directory is "/net/server4a/export/user/Desktop/cell.pex.netlist". When I select the cell view of the device as "Specify SPICE Source File" in Hierarchy Editor, it's always unsuccessful to generate the netlist in ADE. 

A message says:

*Error* _emsGetMsg: argument #3 should be an integer (type template = "ooxtl") - "EMS_ERROR"

Does anyone have the same problem? What's this mean?

Hello All, 

In the virtuoso schematic view, I'm unable to swap the instance with a different one, particularly when placing a device from the TSMC 65 library. Any suggestions on how to approach this?

Regards,

For the XF analysis I would like to only save a certain number of sources.

I have set "save" to "selected" but no matter what I do, all of the sources are saved and the log will print.

No outputs were found. Loosening output filter criterion to `allpub'.

I have tried every variation of the "save" statement in the input files but I cannot get anything to work.

Hi,

I'm current running aging simulation in adexl. After running a 0.5-year DC stress simulation on an inverter, I've got the aging data in a .ba0 file. 

And I'm conducting another simulation for the inverter to check the effect of aging, but I'm confused about which file to load as the stress file from the previous simulation:

My virtuoso version is 6.1.8, thanks for help!

Best,

Holz

Hello! In post-layout simulation, I set some subcircuits to calibre (modeshift4 and SAR_logic9).

To accelerate simulation, I use XPS MS and enable post-layout-optimization:

After simulation, I find tran simulation results are not saved.

But if I disable post-layout-simulation, tran simulation results are saved successfully. What's even more strange is that if I set SAR_logic9 to none and only leave modeshift4 as calibre, then the results of tran simulation can be saved whether post-layout-optimization is enabled or not.

After repeated attempts, I find that as long as SAR_logic9 is set to calibre and post-layout-optimization is enabled, the results of tran simulation can not be saved.

What could be the reason for this?  What could be the problem with SAR_logic9  that causes such a strange phenomenon？

Thank you!

Spectre.out is as follows:

Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 15.1.0.284.isr1 64bit -- 12 Nov 2015
Copyright (C) 1989-2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: vmware Host: vmware.silicon HostID: 7F0100 PID: 46395
Memory available: 23.3686 GB physical: 33.6546 GB
Linux : CentOS release 6.10 (Final)
CPU Type: 12th Gen Intel(R) Core(TM) i7-12700
All processors running at 2112.0 MHz
Socket: Processors
0: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
10, 11

System load averages (1min, 5min, 15min) : 2.5 %, 0.9 %, 0.8 %
This is a virtual machine

Simulating `input.scs' on vmware.silicon at 3:47:27 AM, Sun Feb 25, 2024 (process id: 46395).
Current working directory: /sim/vmware/Rmeasure8_L2_tb2/spectre/config/netlist
Command line:
/eda/cadence/MMSIM151/tools.lnx86/bin/spectre -64 input.scs \
+escchars +log ../psf/spectre.out -format psfxl -raw ../psf +ms \
+speed=3 +aps +postlayout +lqtimeout 900 -maxw 5 -maxn 5

Loading /eda/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /eda/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ...
Loading /eda/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /eda/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /eda/cadence/MMSIM151/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file: /sim/vmware/Rmeasure8_L2_tb2/spectre/config/netlist/input.scs
Reading file: /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/configs/ms#3.cfg
Reading file: /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/configs/ms.cfg
Reading file: /home/vmware/IC_project/tsmc18mm_1.8v_3.3v_T-018-CM-SP-007-K3_IC61_bsim4.5_pdk_v1.3a_20170119_cfg_2_2/t018cmsp007_1_4p1/T-018-CM-SP-007/models/cmn018_assp_v1d4p1_myusage.scs
Reading file: /home/vmware/IC_project/tsmc18mm_1.8v_3.3v_T-018-CM-SP-007-K3_IC61_bsim4.5_pdk_v1.3a_20170119_cfg_2_2/t018cmsp007_1_4p1/T-018-CM-SP-007/models/cmn018_assp_v1d4p1.scs
Reading file: /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/configs/digital.cfg
Reading file: /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/configs/analog.cfg
Reading file: /home/vmware/IC_project/R_measure/my_codecell/datastore_8_20/veriloga/veriloga.va
Reading file: /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading file: /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Time for NDB Parsing: CPU = 1.05784 s, elapsed = 1.07502 s.
Time accumulated: CPU = 1.06684 s, elapsed = 1.07502 s.
Peak resident memory used = 129 Mbytes.

The CPU load for active processors is :
Spectre 0 (1.9 %) 1 (99.1 %) 2 (3.7 %)
Other
The simulator has reused the existing Verilog-A libraries for this simulation run. If you do not want to use these libraries, set the 'CDS_AHDL_REUSE_LIB' environment variable to 'NO' and rerun the simulation.
Reusing Verilog-A library /sim/vmware/Rmeasure8_L1_tb6/spectre/schematic/netlist/input.ahdlSimDB/057c7a69d261cc6b6e4ba21b94d3b817.datastore_8_20.ahdlcmi/Linux-64/obj/optimize/5.0/libahdlcmi_datastore_8_20.so.
Existing shared object for module datastore_8_20 is up to date.
Installed compiled interface for datastore_8_20.

Warning from spectre during circuit read-in.
WARNING (SFE-2649): Remove instance `R8<1>' in subckt `RDAC5_L1' because its terminals are connected together.
WARNING (SFE-2649): Remove instance `R8<2>' in subckt `RDAC5_L1' because its terminals are connected together.
WARNING (SFE-2649): Remove instance `R8<3>' in subckt `RDAC5_L1' because its terminals are connected together.
WARNING (SFE-2649): Remove instance `R8<4>' in subckt `RDAC5_L1' because its terminals are connected together.
WARNING (SFE-2649): Remove instance `R8<5>' in subckt `RDAC5_L1' because its terminals are connected together.
Further occurrences of this warning will be suppressed.

Reading link: /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading link: /eda/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.h
Reusing Verilog-A library /sim/vmware/AFE5_wPAD_tb4/spectre/schematic/netlist/input.ahdlSimDB/bsource_d0e2ae.va.bsource_d0e2ae.ahdlcmi/Linux-64/obj/optimize/5.0/libahdlcmi_bsource_d0e2ae.so.
Existing shared object for module bsource_d0e2ae is up to date.
Installed compiled interface for bsource_d0e2ae.
Reusing Verilog-A library /sim/vmware/AFE5_wPAD_tb4/spectre/schematic/netlist/input.ahdlSimDB/bsource_rppoly_c38538.va.bsource_rppoly_c38538.ahdlcmi/Linux-64/obj/optimize/5.0/libahdlcmi_bsource_rppoly_c38538.so.
Existing shared object for module bsource_rppoly_c38538 is up to date.
Installed compiled interface for bsource_rppoly_c38538.
Reusing Verilog-A library /sim/vmware/AFE5_wPAD_tb4/spectre/schematic/netlist/input.ahdlSimDB/bsource_c7f949.va.bsource_c7f949.ahdlcmi/Linux-64/obj/optimize/5.0/libahdlcmi_bsource_c7f949.so.
Existing shared object for module bsource_c7f949 is up to date.
Installed compiled interface for bsource_c7f949.
Reusing Verilog-A library /sim/vmware/AFE5_wPAD_tb4/spectre/schematic/netlist/input.ahdlSimDB/bsource_cb75ce.va.bsource_cb75ce.ahdlcmi/Linux-64/obj/optimize/5.0/libahdlcmi_bsource_cb75ce.so.
Existing shared object for module bsource_cb75ce is up to date.
Installed compiled interface for bsource_cb75ce.
Time for Elaboration: CPU = 2.10268 s, elapsed = 2.1022 s.
Time accumulated: CPU = 3.17052 s, elapsed = 3.17735 s.
Peak resident memory used = 347 Mbytes.

Starting APS DC ...

Warning from spectre during hierarchy flattening.
WARNING (SPECTRE-18018): Analyses 'info' are not yet supported in 'Spectre XPS Mixed-signal Mode'.
WARNING (SPECTRE-18018): Analyses 'info' are not yet supported in 'Spectre XPS Mixed-signal Mode'.
WARNING (SPECTRE-18018): Analyses 'info' are not yet supported in 'Spectre XPS Mixed-signal Mode'.
WARNING (SPECTRE-18018): Analyses 'info' are not yet supported in 'Spectre XPS Mixed-signal Mode'.
WARNING (SPECTRE-18018): Analyses 'info' are not yet supported in 'Spectre XPS Mixed-signal Mode'.
Further occurrences of this warning will be suppressed.

Time for EDB Visiting: CPU = 1.27881 s, elapsed = 18.4091 s.
Time accumulated: CPU = 46.4279 s, elapsed = 24.6789 s.
Peak resident memory used = 690 Mbytes.

Notice from spectre.
102 warnings suppressed.

Digital Detection Vsource and Virtual Power Supply Node Summary:
Type #CC #Bulk Voltage Name
GND 4388 8926 0 0
Possible VGND 415 689 TBD AVSS
Possible BUS 410 438 TBD I3.AVDD
VPN 4298 5913 TBD I3.DVDD

To force a virtual power or ground node, add in netlist
optVPN options ms_vpn=[node_name vpn_voltage]
optVGND options ms_vgnd=[node_name]
use keyword auto_vpn if you do not know the vpn_voltage

Warning from spectre.
WARNING: 2 nodes have no driver
Notice from spectre during topology check.
No connections to node `I3.CLK'.
No connections to node `I3.D<0>'.
No connections to node `I3.EN_work'.
No connections to node `I3.FCDin'.
No connections to node `I3.I0.I0.I6.c_6150_n'.
Further occurrences of this notice will be suppressed.
Only one connection to the following 162 nodes:
Dout1<1>
Dout1<2>
Dout1<3>
Dout1<4>
Dout1<5>
Further occurrences of this notice will be suppressed.
No DC path from node `I3.CLK' to ground, Gmin installed to provide path.
No DC path from node `I3.D<0>' to ground, Gmin installed to provide path.
No DC path from node `I3.EN_work' to ground, Gmin installed to provide path.
No DC path from node `I3.FCDin' to ground, Gmin installed to provide path.
No DC path from node `I3.I0.I0.I6.c_6150_n' to ground, Gmin installed to provide path.
Further occurrences of this notice will be suppressed.
Parasitics Reduction Enabled.
(Resistors reduced by 86.78% Capacitors reduced by 53.84%).

Global user options:
reltol = 0.0001
vabstol = 1e-06
iabstol = 1e-12
temp = 27
gmin = 1e-12
rforce = 1
maxnotes = 5
maxwarns = 5
digits = 5
cols = 80
pivrel = 0.001
sensfile = ../psf/sens.output
checklimitdest = psf
save = selected
tnom = 27
scalem = 1
scale = 1

Scoped user options:
cktpreset = digital subckt=my_DPAD3
cktpreset = digital subckt=digital1
cktpreset = analog subckt=R_array3
cktpreset = analog subckt=my_APAD4
cktpreset = analog subckt=Ibias_gen4_L2
cktpreset = analog subckt=Icopy_select1_L2
cktpreset = analog subckt=OPA4_DAC1_L2_D1_SW4
cktpreset = analog subckt=SW3_L2
cktpreset = analog subckt=OPA8_DAC2_L1_SW4
cktpreset = analog subckt=BDI8_L1
cktpreset = analog subckt=RDAC5_L1
cktpreset = analog subckt=DEL4BWP7T
cktpreset = analog subckt=stcomparator6_select4_L1

Circuit inventory:
nodes 91841
bsim4 22208
bsource_c7f949 8
bsource_cb75ce 10
bsource_d0e2ae 906
bsource_rppoly_c38538 453
datastore_8_20 1
diode 258
inductor 17
vsource 44
capacitor 161953
resistor 82177

Analysis and control statement inventory:
dc 1
info 8
tran 1

Output statements:
.probe 0
.measure 0
save 1

Notice from spectre.
Multithreading Enabled: 8 threads in the system with 12 available processors.
Spectre XPS Mixed-signal Mode Enabled ( speed=3 ).

Time for parsing: CPU = 40.0209 s, elapsed = 36.5208 s.
Time accumulated: CPU = 60.4128 s (1m 0.4s), elapsed = 39.2277 s.
Peak resident memory used = 958 Mbytes.

~~~~~~~~~~~~~~~~~~~~~~
Pre-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~
- MS Table model. VDD=1.8V used for XPS table model creation, to overwrite
tmopt options vdd=val
- MS Circuit partitions: 60.1% transistors and 28.5% nodes are identified as digital partitions.
One of the following solutions may improve the digital detection.
Manually define internal digital power supply nodes and voltages.
opt1 options ms_vpn=[VDD_DIG 1.2 VDD_DIG1 3.3]
opt2 options ms_vgnd=[VSS]
For complex device models use the MS macro model option.
opt3 options macro_mos=[pmos_subckt nmos_subckt]
Use the cktpreset=digital option to force subcircuits into digital.
opt4 options cktpreset=digital subckt=[subckt_def_name]
opt5 options cktpreset=digital inst=[subckt_inst_name]
~~~~~~~~~~~~~~~~~~~~~~

Warning from spectre.
WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format.
Notice from spectre.
205 notices suppressed.
Warning from spectre.
WARNING (SPECTRE-16830): The 'dcOp' analysis of type 'dc' is skipped in XPS flow.
WARNING (SPECTRE-16518): Arithmetic exception in analysis `dcOp' .

Total time required for dc analysis `dcOp': CPU = 0 s, elapsed = 97.0364 us.
Time accumulated: CPU = 60.4128 s (1m 0.4s), elapsed = 39.2283 s.
Peak resident memory used = 959 Mbytes.

Reading file: /sim/vmware/Rmeasure8_L2_tb2/spectre/config/netlist/input.apsdc

Warning from spectre during read of ic file `./input.apsdc'.
WARNING (SPECTRE-8301): line 479: Unknown node `I3.I0.I0.I2.I0.I0.I2.I0<1>.M1:int_d' will be ignored.
WARNING (SPECTRE-8301): line 480: Unknown node `I3.I0.I0.I2.I0.I0.I2.I0<1>.M1:int_s' will be ignored.
WARNING (SPECTRE-8301): line 481: Unknown node `I3.I0.I0.I2.I0.I0.I2.I0<1>.M2:int_d' will be ignored.
WARNING (SPECTRE-8301): line 482: Unknown node `I3.I0.I0.I2.I0.I0.I2.I0<1>.M2:int_s' will be ignored.
WARNING (SPECTRE-8301): line 483: Unknown node `I3.I0.I0.I2.I0.I0.I2.I0<1>.M8:int_d' will be ignored.
Further occurrences of this warning will be suppressed.

Time for dc init: CPU = 390.941 ms, elapsed = 390.908 ms.
Time accumulated: CPU = 60.8358 s (1m 0.8s), elapsed = 39.6516 s.
Peak resident memory used = 960 Mbytes.

Opening the PSFXL file ../psf/tran.tran.tran ...

***********************************************
Transient Analysis `tran': time = (0 s -> 1 us)
***********************************************

Notice from spectre at time = 0 s during IC analysis, during transient analysis `tran'.
There are 90878 IC nodes defined.
Warning from spectre at time = 0 s during IC analysis, during transient analysis `tran'.
WARNING (SPECTRE-16686): Initial condition of 0 A on node I10:Dout1[1]_VSS_flow converted into initial guess (nodeset). Initial conditions will only be accepted for inductor currents.
WARNING (SPECTRE-16686): Initial condition of 0 A on node I10:Dout1[2]_VSS_flow converted into initial guess (nodeset). Initial conditions will only be accepted for inductor currents.
WARNING (SPECTRE-16686): Initial condition of 0 A on node I10:Dout1[3]_VSS_flow converted into initial guess (nodeset). Initial conditions will only be accepted for inductor currents.
WARNING (SPECTRE-16686): Initial condition of 0 A on node I10:Dout1[4]_VSS_flow converted into initial guess (nodeset). Initial conditions will only be accepted for inductor currents.
WARNING (SPECTRE-16686): Initial condition of 0 A on node I10:Dout1[5]_VSS_flow converted into initial guess (nodeset). Initial conditions will only be accepted for inductor currents.
Further occurrences of this warning will be suppressed.
WARNING (SPECTRE-16255): Initial condition of 3.48554 nV between nodes I3.CLK and 0 converted into initial guess (nodeset) because there is no capacitive path to ground.
WARNING (SPECTRE-16255): Initial condition of 3.48554 nV between nodes I3.D<0> and 0 converted into initial guess (nodeset) because there is no capacitive path to ground.
WARNING (SPECTRE-16255): Initial condition of 3.48554 nV between nodes I3.EN_work and 0 converted into initial guess (nodeset) because there is no capacitive path to ground.
WARNING (SPECTRE-16255): Initial condition of 3.48554 nV between nodes I3.FCDin and 0 converted into initial guess (nodeset) because there is no capacitive path to ground.
WARNING (SPECTRE-16255): Initial condition of 3.48554 nV between nodes I3.I0.I0.I3.c_22536_n and 0 converted into initial guess (nodeset) because there is no capacitive path to ground.
Further occurrences of this warning will be suppressed.

Finding DC approximate solution failed. Try again with try_fast_op set to no.
Trying Fast DC for nodesets..

***** First stage DC finished in 0.057 sec
DC simulation time: CPU = 2.97655 s, elapsed = 1.36009 s.
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 1 us
step = 1 ns
maxstep = 10 ns
ic = all
useprevic = no
skipdc = no
reltol = 10e-06
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = conservative
method = trap
lteratio = 10
relref = alllocal
cmin = 0 F
gmin = 1 pS
rabsshort = 1 mOhm

Output and IC/nodeset summary:
save 8 (current)
save 373 (voltage)

tran: time = 26.5 ns (2.65 %), step = 10 ns (1 %)
tran: time = 76.5 ns (7.65 %), step = 10 ns (1 %)
tran: time = 126.5 ns (12.6 %), step = 10 ns (1 %)
tran: time = 176.5 ns (17.6 %), step = 10 ns (1 %)
tran: time = 226.5 ns (22.6 %), step = 10 ns (1 %)
tran: time = 276.5 ns (27.6 %), step = 10 ns (1 %)
tran: time = 326.5 ns (32.6 %), step = 10 ns (1 %)
tran: time = 376.5 ns (37.6 %), step = 10 ns (1 %)
tran: time = 426.5 ns (42.6 %), step = 10 ns (1 %)
tran: time = 476.5 ns (47.6 %), step = 10 ns (1 %)
tran: time = 526.5 ns (52.6 %), step = 10 ns (1 %)
tran: time = 576.5 ns (57.6 %), step = 10 ns (1 %)
tran: time = 626.5 ns (62.6 %), step = 10 ns (1 %)
tran: time = 676.5 ns (67.6 %), step = 10 ns (1 %)
tran: time = 726.5 ns (72.6 %), step = 10 ns (1 %)
tran: time = 776.5 ns (77.6 %), step = 10 ns (1 %)
tran: time = 826.5 ns (82.6 %), step = 10 ns (1 %)
tran: time = 876.5 ns (87.6 %), step = 10 ns (1 %)
tran: time = 926.5 ns (92.6 %), step = 10 ns (1 %)
tran: time = 976.5 ns (97.6 %), step = 10 ns (1 %)
Number of accepted tran steps = 104

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Post-Transient Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- DC analysis takes more than half of total simulation time. To speed up, consider
add +fastdc on command line
add +msdc=ms on command line
reuse previous ic file
- Non-default settings that could significantly slow down simulation
errpreset = conservative, default moderate
reltol = 10e-06, default 100e-06 (conservative)
- 94.13 % simulation time spent in analog partition. Consider force more circuit blocks to digital, or use more aggressive APS options.
5.87 % simulation time spent in digital partition.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

During simulation, the CPU load for active processors is :
Spectre 0 (19.0 %) 1 (65.0 %) 2 (24.0 %) 3 (32.7 %)
4 (14.2 %) 5 (12.0 %) 6 (12.0 %) 7 (12.0 %)
8 (5.4 %) 9 (4.1 %) 10 (2.2 %)
Other
Initial condition solution time: CPU = 2.97655 s, elapsed = 1.3602 s.
Intrinsic tran analysis time: CPU = 2.85357 s, elapsed = 1.34089 s.
Total time required for tran analysis `tran': CPU = 6.77197 s, elapsed = 4.59517 s.
Time accumulated: CPU = 67.1968 s (1m 7.2s), elapsed = 43.8328 s.
Peak resident memory used = 1.06 Gbytes.

Notice from spectre.
709 warnings suppressed.

Aggregate audit (3:48:11 AM, Sun Feb 25, 2024):
Time used: CPU = 67.2 s (1m 7.2s), elapsed = 43.8 s, util. = 153%.
Time spent in licensing: elapsed = 47.2 ms.
Peak memory used = 1.06 Gbytes.
Simulation started at: 3:47:27 AM, Sun Feb 25, 2024, ended at: 3:48:11 AM, Sun Feb 25, 2024, with elapsed time (wall clock): 43.8 s.
spectre completes with 0 errors, 32 warnings, and 24 notices.

Tool: Cadence Virtuoso ICADVM20.1-64b.500.27,  ADE Assembler - Maestro 

My single-point DC simulations work fine and all the expressions (i.e. OP("/P0" "gm") etc.) work fine. However, when I try to do the variablesweep DC simulation, I get the "eval error" for the expression evaluation of Operating point sweep (OS) parameters. I checked the 'Expression Evaluation Log' by right-clicking the 'eval err' > 'view log messages' and it shows " *Error* eval: undefined function - ciwMenuInit" (see attached screenshot below)

My expression consists of the following OP parameters: 

OS("/P0" "gm") 

OS("/P0" "vth")

OS("/P0" "gds")

OS("/P0" "cds")

etc. 

All the DC sweep simulations finish fine without any simulation errors as monitored through the simulation log window (also shown in the attached screen shown above). 

I noticed very unsual behavior as follows: When I click on the red colored 'eval err' of any expression such as OS("/P0" "gm"), it will in fact show the correct results in a plot. I confirmed this from the result browser. So, I believe, the expression was evaluated but somehow still labels it as 'eval err'.

Another weird thing I noticed is that when I include the DC variable sweep simulations, it also shows 'eval err' for all the other expressions NOT associated with DC sweep as well. For example, having as simple as (2+2) shows up with 'eval err'. However, when I remove the DC sweep simulation and their associated expressions, the rest of the expressions work fine (i.e. (2+2) would print 4. 

Let me know how to overcome this weird error. thanks!

Dhruv Patel