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Error while simulating a project on ADE(XL)

August 12, 2021, 11:54 pm
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Hello. I have recently purchased the license of cadence tools and we have installed tools and configure license file successfully. While running the simulation for a simple CMOS inverter i get the following error. There is no error in the designing part. however, while simulating I get the following error on the virtuoso log window.

For more details, consult the job log file:

/mnt/cadence_tools/logs_root/logs0/Job4.log

ERROR (ADEXL-5031): While simulating run Interactive.2, point 1, test Projects:CMOSINVERTER_TB:1, received error:

Simulation Error:

------------------------------

Simulator failed to complete the simulation.

The simulator process returned a non-zero exit code, indicating failure.

The simulator could have crashed or intentionally returned to indicate an error.

Check the simulator log file for more information. Common causes:

1. Simulator may have crashed during exit even after reporting success in log file.

2. Abrupt automatic simulator termination (e.g., SIGKILL) because the simulator process has

exceeded resource limits, which can be specified in the distribution system or

by the kernel itself (e.g., the Linux OOMKiller).

3. Manual termination of the simulator process.

./runSimulation can be manually run in this directory to check the issue.

I looked through the path "/mnt/cadence_tools/logs_root/logs0/Job4.log" and it showed the following errors

ERROR (ADE-5704): Variable 'options faultanalysis' is either not declared or does not exist
        for analysis 'tran'.
ERROR (ADE-5704): Variable 'options faultInfoAnalysis' is either not declared or does not exist
        for analysis 'tran'.
ERROR (ADE-5704): Variable 'options faultDoSampling' is either not declared or does not exist
        for analysis 'tran'.
      ...successful.
ERROR (ADE-5704): Variable 'options faultanalysis' is either not declared or does not exist
        for analysis 'tran'.
ERROR (ADE-5704): Variable 'options faultanalysis' is either not declared or does not exist
        for analysis 'tran'.

ERROR (ADE-5704): Variable 'options faultDoSampling' is either not declared or does not exist
        for analysis 'tran'.
ERROR (ADE-5704): Variable 'options faultDoSampling' is either not declared or does not exist
        for analysis 'tran'.
ERROR (ADE-3036): Errors encountered during simulation. The simulator run log has not been generated.
        Possible cause could be an invalid command line option for the version of the simulator
        you are running. Choose Setup->Environment and verify that the command line options
        specified in the userCmdLineOption field are supported for the simulator.
        Alternatively, run the simulator standalone using the runSimulation file in the netlist
        directory to know the exact cause of the error.
INFO (ADEXL-1654): Simulator 'spectre' doesn't provide simulation failure
        information at the analysis level. So 'SkipFailedAnalyses' for option
        'evalOutputsOnSimFailure' wouldn't work for this simulator.

Kindly if someone could help me rectify this problem, i will be grateful

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Generating Liberty (.lib) File From Verilog-A Table Model

August 20, 2021, 3:40 am
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Hello,

I want to create a liberty file for a new technology that I have access to verliog-A table model using Cadence Liberate. I can't find any guidance in the Liberate documents. Is it possible to use the Verilog-A model instead of the Spice model to create a liberty file using Cadence Liberate? Can anyone help me with how I can do that?


Many Thanks

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Selecting shapes contained in/inside shape

August 20, 2021, 2:45 pm
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Hi,

I am looking for a way to select all shapes contained within another shape.

I have a list of candidate shapes and I want to test to see which ones are inside a polygon shape (in this case an annular gate polygon).

So far I have:

geSelectArea(window_id gate_shape~>points gate_shape~>objType)
gatecont_shapes=geGetSelectedSet(working_cellview)
geDeselectAll(window_id)

I don't really want to select and deselect as this might clear selections that have already been made. Is there a way to do this outside of the graphic editor suite of commands?

Another issue with this is that it selects everything within the polygon (not just a candidate shape). I could filter the list, but given the above issue (selection in GE), it's somewhat a secondary problem.

Thanks.

Art

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Double sided spectrum in PSS simulation

August 21, 2021, 11:07 pm
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Hello,

I am curious, If we can plot double sided spectrum (freq axis also having -ve range) in PSS analysis.

If so, How to do that ?

Thanks in advance

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How to snap different layers to the edges of other layers? (Virtuoso Layout XL)

August 22, 2021, 1:09 am
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So I used to work with Tanner L-edit and it had this beautiful mouse snapping, where the mouse would snap at the edges/center/corners of another layer/instance so I could easily draw layers and end where I wanted.

But in layout XL, If I have a Metal 1 and I draw another M1 it will auto snap and complete the connection, but if I draw Metal 2 on top of the M1 it does not snap anywhere, and I have to zoom in close to see whether it is going to align with the edge of the metal 1 or not ( see pic above)

Is there any easier way to do rather than zooming and seeing whether my metal has aligned to the edge or not?

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Frequency Measurement when clock is constant (veriloga)

August 23, 2021, 9:35 am
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Hello All,

I am trying to create a model which is dependent on the frequency of the input signal clkA_in3m.

I am using the model "Frequency measurements (dg-vams4-8)." as a reference:

designers-guide.org/.../index.html

The relevant part of the code is below.

//****** Frequency Measurement **********
t = last_crossing(V(clkA_in3m) - thresh, +1);
@(cross(V(clkA_in3m) - thresh, +1)) begin
if (timing) begin
period = t - t0;
freq = 1/period;
Req2 = k/freq;
end
t0 = t;
timing = 1;
end

The frequency measurement works pretty well. I then use "freq" to adjust the value of another variable, let's say "Req2".
The problem that I have if that if the clock signal remains constant the variable "freq" keeps showing the same last value which is wrong and then my variable "Req2" remains constant which is also wrong.
I know that the reason is because there are no clocks. How can I make the "freq" to update to a predefined value, let's say 0.1 (Hz) in such a scenario?
Thank you very much for your help.

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How to keep attached shapes of a multipart path when chopping the multipart path

August 24, 2021, 12:29 am
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Hi,

I create a multipart path and some shapes attached to it.

However,those attached shapes get lost when I chop the metal of the multipart path.

I wonder how to keep those shapes attached to the multipart path ring.

Great appreciate if anybody help me.

Strongy

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Disable "copy to cellview" option in ADE Variables

August 24, 2021, 7:03 am
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Hi,

Is it possible to disable "copy to cellview" option in ADE Variables using Skill or any other way?

Thanx

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SPICEIN: How to import mutual inductance K?

August 25, 2021, 3:25 am
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Hi,

I am using SPICEIN to import a SPICE netlist to a schematic. The SPICE netlist contains resistor, capacitor, inductance and mutal inductance.

I am using a deviceMap file.

Resistor, capacitor and inductance gets imported well but not mutual inductance.

I do not know how to fill the deviceMap file for mutual inductor.

Any idea?

Alex

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skipping digital registers in analog extracted simulations

August 25, 2021, 5:29 am
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Hallo, 

I would like to simulate my design after layout. My design consists of a big analog part and a lot of shift registers that are used to configure the analog part.

Now I finished the layout of all components including analog and registers together. When performing analog extracted using quantus of the top level I can not longer configure the value of the registers since I can no longer set the cell view to veriloga in the config. Therefore I can only simulate the system with registers have a value of zero. 

Is there is a way to generated an analog extracted view without flattening the registers as well.

Thanks and regards

Mohammad

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Regarding cadence virtuoso installation

August 25, 2021, 8:14 am
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I am new to Linux and trying to install cadence virtuoso (Base & Hotfix IC618 ) in CentOS 8 system. I wrote the bashrc file as below but was unable to access the virtuoso software. Please somebody help me.

export CDS_Netlisting_Mode="Analog"
export CDS_AUTO_64BIT="All"
#export QRC_EXTRACTION_ENABLE
export CDS_LIC_FILE=5280@xxx xxx xxx


# Set up IC (change for Cadence 5 or 6)
export CDS=/root/cadence/installs/IC618
export PATH=$CDS/tools/bin:$CDS/tools/dfII/bin:$CDS/bin:$CDS/share/bin$
export LD_LIBRARY_PATH=$CDS/tools/lib/64bit:$CDS/tools/dfill/lib/64bit

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Relative path for Ocean script in Maestro

August 25, 2021, 2:04 pm
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Hello,

I have an Ocean script, which I added to my output setup in maestro. When I added the script from a local folder, it got copied to the 'ScriptDir' within the maestro cell view directory. The path to it was also updated in the maestro expression for the script. However, it added the absolute path to the script, which might change, eg. when the cell is checked-in into a revision system.

The fact, that the script is copied to the 'ScriptDir' is not the problem, it is actually good, because this way it is always together with the maestro view. However, the path to it must be relative to location of the maestro view. How can I achieve this?

Best regards

Paul

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How to run encrypted Pspice model in Cadence?

August 26, 2021, 11:38 pm
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Can anyone please help me on how to run encrypted pspice model in cadence?

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Setting up a jitter simulation for Ring Oscillator

August 28, 2021, 5:08 am
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Hi,

I am designing a programmable CMOS ring oscillator in Virtuoso ICADV12.3-64b environment.

By using different digital control settings, I can choose the odd number of inverters in the ring correspondingly.

Aim is to find out the ways that they can affect the periodicity.

I was able to get the time periods for each ring across the process, supply voltage, temperature variations. And also with help of Monte-Carlo simulations I was able to find the standard deviation of the time period.

I wanted to know what are the other possibilities that they can affect the periodicity. I think one is the random jitter.

I guess to find out the amount of jitter for the ring oscillator, pss + pnoise is the way. Correct me if I am wrong.

 

Some questions:

  1. Why are there two separate analysis PSS, PNOISE to measure Jitter ? And What do they do  ?

PSS:

  1. Shooting or Harmonic balance , which is most preferrable for RO based designs and why ?
  2. Is Beat frequency equal to frequency of RO ? If I just choose 'Auto calculate' will the tool be able to pick up correct RO frequency ?
  3. What is the safe and best value for to choose number of harmonics ? Does it vary with the different RO frequencies ?

PNOISE:

  1. What does 'Output frequency range'  do in the PNOISE simulations ?
  2. Noise type 'Jitter' -> is it the random phase jitter of clock ?
  3. Are the number of sidebands in PNOISE should be equal to number of harmonics defined in the PSS ?

 

I am new to run these set of simulations.

Could you please throw some light on how to get started and please help me in this regard ?

 

Thanks & Regards,

Harish

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[Virtuoso layout XL] How to switch between quick align User Spacing and quick align No Spacing with single keystroke?

August 30, 2021, 1:03 am
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So currently I have to do A>F3>use mouse to select No Spacing or User Spacing and then align, but I switch between them pretty often and it looks like if there was a bindkey for switching them it would be alot better. Is there any way? ( Sorry I don't have any SKILL knowledge, so please help me out on this )

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DC Convergence Problem When Simulating a Post-Layout r_c and r_c_cc Extraction

August 30, 2021, 2:07 pm
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Hi All,

I'm simulating a post layout r_c and r_c_cc extraction of a transmitter circuit for transient simulation using config view, The problem is when simulation starts it checks for the "Trying 'homotopy = dpptran' for initial conditions" and made several attempts before it fails like after 4-5 hours. I also tried with loosening the vabstol and iabstol to relaxed values than the default value. But nothing works. For c_cc extraction the post layout simulation worked fine and no such error appeared for the same circuit. My transient simulation run setting is "Liberal" and there is one ideal constant current source apart from supply and control signals. Im using cadence IC6.1.8-64b.83 amd MMSIM 20.1.0.068. I have used Calibre v2021.3_15.9 for the c_cc, r_c and r_c_cc extraction. The snippet of the output log is attached. Can anyone help me with it.

Thanks!

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Could anyone explain this sampled noise simulation result

August 31, 2021, 1:03 am
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Hi, I'm learning sampled circuit noise simulaton, pss+pnoise, start with the simplest S/H circuit.

- Simulator, Spectre 19.1

- TestBench (fig1), a switch-capacitor S/H circuit, as switch sampling frequency 400KHz >> RC frequency 27KHz, no alising should happen.

- Pnoise Setup (fig2), sampled noise, sampled phase, 2 outputs with Vc and Vn2

- Results (fig3). For density, Vc is twice larger than Vn2; while for EBW, Vn2 is twice larger than Vc.

Though the total noise of Vc and Vn2 are same, but the bandwidth and density are different.

I think Vn2 is more reasonable, the densisty and bandwidth are exactly what I calculate, but how to explain Vc? Could anyone help? thank you!

Pnoise

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Navigator net highlight/probe and navigator net 'XL status' issue

August 31, 2021, 6:37 am
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(1) When selecting a net from navigator or probing that net,  it does not highlight the all the shapes that is connected to the net(the ones that are 1-2 levels below). I tried tinkering around with 'Extract layout' settings and setting the 'Extract connectivity to level: 0' and changing the 0 to something like 2-5 and even 32(max) and checking the options as well, but I din't see any useful results. This is troublesome because i need to see all metal shapes connected to a net.

(2) Right of the net name in navigator we have 'XL status'. Usually extracting the connectivity to 2-5 levels solves the incorrectly shown opens/shorts but often times it does not ( As shown in the picture - The cell is LVS clean but it still says some nets are open), how to make it such that the status is 'no markers' for all nets?

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ADE Assembler - calcVal + Monte Carlo + Reusing Trim Codes in new MC for characterization

September 1, 2021, 5:52 am
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Hi,

I am simulating a calibrated circuit in ADE Assembler. I have Virtuoso version ICADVM18.1-64b.500.13. 

Simulation Method:

I run two tests for each Monte Carlo sample--one for finding the right trimming code at typical conditions and another for characterizing the trimmed circuit at different vdd & temperature conditions. Normally, I pass the trim code from one test to another using "calcVal" and it works fine.

My problem:

I ran a Monte Carlo with 100s of samples at a specific seed, found the trim code for each sample, used it to characterize the circuit at some combinations of vdd & temperature. Now I would like to perform calibration at vdd/temp conditions different from the previous ones while reusing the trim codes from the completed MC simulation. I am choosing the same MC setting (seed, number of samples, etc).

I tried using calcVal + historyName with matchParams as dicussed here Error During Using calcVal for Calibration and Performing Temperature Sweep - Custom IC Design - Cadence Technology Forums - Cadence Community, but it did not work. I have been referring to the calcVal RAK document, so I tried also adding getFirstSweepPoint. 

It did not work with the following: 

calcVal("trim_code" "test_trim" ?historyName "MonteCarlo.1" ?matchParams list(list("temperature" "27")))

calcVal("trim_code" "test_trim" ?historyName "MonteCarlo.1" getFirstSweepPoint t ?matchParams list(list("temperature" "27")))

calcVal("trim_code" "test_trim" ?cornerName "state_mc" ?historyName "MonteCarlo.1" getFirstSweepPoint t ?matchParams list(list("temperature" "27")))

1. I have the trim codes and other parameters value that I would like to pass in a file. Is there a way to call these values during MC simulation from the file? 

2. I can add these trim codes and other parameters that I would like to pass to the design variables as a list. Is there a way to match the MC iteration with the list of design variable/s like we do when creating parametric sets?

Any other solution is appreciated. Thank you.

Fikre

 

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Weird behavior on "save" statements.

September 1, 2021, 9:47 am
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I have the following analyses defined.

tran tran stop=10n infonames=[dcnode] infotimes=[0.1n 9.9n 30.9n] infotime_pair=no save=selected
dcnode info what=oppoint where=rawfile save=selected

My save statements are commented.

//save vddd
//save *:d,*:g,*:s,*:b devtype=pch

The only other save statement in the netlist is

saveOptions options save=selected

I assume nothing should be saved in the info analyses because "selected" save statements asks to save nothing.

But it looks like I have the operating points saved on all the devices.

Any pointers would be very welcome.

Thanks much!

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