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2021-Era Recommended Spectre "Measure" Syntax

August 6, 2021, 3:02 pm
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Greetings - 

What is Cadence's modern-day (circa 2021) recommendation for scalar measurements in Spectre netlists?
(Something akin to traditional-SPICE's `.meas` cards.) 

This would be something that produces: 
* A single number for "regular" / scalar analyses (dc, tran, all the usuals) 
* An array of numbers for `montecarlo` and `sweep`
* (Maybe something, maybe not, you tell me, for anything else - nested sweeps, RF analyses, noise contributions, whatever)

I hear SpectreMDL has been de-emphasized and/or deprecated. 
And I see the current help for `montecarlo` recommends this: 

```
mc1 montecarlo variations=process seed=1234 numruns=200 {
  tran1 tran start=0 stop=1u // another child analysis
  export slewrate=oceanEval("slewRate(v(\"vout\"),10n,t,30n,t,10,90 )")  // <= this here 
}
```

So that's a combination of the `export` keyword (which I don't see in the help docs) and `oceanEval` (same).
Is that the standing recommendation? 
Or is there something else Cadence would advocate instead? 

(And I am really, really uninterested in answers involving the ADE.) 
Thanks!
Dan

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Adding shortcuts For probing or any feature

August 7, 2021, 3:37 am
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Hi All ,

I am using cadence virtuoso version IC618, i want to add the shortcut that when i press "9" the selected net gets probed , I don't know where exactly to make changes to achieve this. Kindly help me with it.

Thanks

Shubham

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EMX issue

August 7, 2021, 5:18 am
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I am using CADENCE  version IC6.1.1. I have integrated Integrand 10 in the same version.

But while running simulation on an inductor I get the following error 

'EMX interface job exited abnormally with status 1'

Please let me know the probable reason for this or if there is any solution.

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Need Help to write an email into the desiging fonts style

August 10, 2021, 10:08 am
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This community is very unique and here people are very helpful so I am here to ask a question about the fonts style my question is I like stylish font style from Ezzee Fonts and so I want to send an email into the designing font style to my friends its possible if I can do this please tell me about this I love this type of the font style if anyone knows about this, please tell its make very helpful for me

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PLL + PSS + PNOISE convergence

July 26, 2021, 12:21 am
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After reading most of the documentation about how to setup PSS for ring-oscillators, etc. I was able to simulate the ring-VCO with an subsequent div-by-2 in PSS with PNOISE and got reasonable results.

All the blocks are analog (spice/spectre), only the control signals are generated from Verilog-A blocks. I do see some warnings about the Verilo-A blocks.

- fvco=480M, fdiv2=240MHz --> beat-freq=240MHz, conservative, 600 harmonics, tstab=500n

- autonomous circuit: osc-node+ is the ringo-vco output net

- cmin=4fF ( to have not ideal sharp edges)

The next step towards a full PLL feedback loop simulation was to add another div-by-12 frequency divider in series to the div-by-2 --> did not achieve convergence yet, but tested the following settings

- beat-freq=20MHz, tstab=500n, maxstep=1ps (or none)

- osc-node+ is either ringvco-output(480MHz) or fbdiv12-output(20MHz), but none did converge the PSS simulation

- trap vs. gear2only

The Conv norm value is sometimes below 1, but still does not converge.

1. Any idea what I can do to achieve convergence ?

2. A collerague told me (from his experience) to set the beat-freq to 20MHz/3=6.6667MHz, but he could not tell me why this would be advantageous - do you have any idea )

The final goal is to simulate the complete PLL, which will then be a driven circuit with a reference signal (no osc-node+ required).

But first I want to achieve convergence for "ring-vco+divby2+divby12".

Attached is the spectre.out (at least I drag and dropped it into the editor, but cannot see it)  ... ?

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Use Maestro expressions in Ocean script

August 11, 2021, 4:37 am
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Hello,

I have an Ocean script in maestro, which generates some outputs depending on simulation variables. The variables I get with the 'pv(...)' function, but I also want to use some other expressions I defined in the 'Outputs Setup'. Is this possible? I can't find an example for it.

Best regards

Paul

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can't rerun unfinished /error points

August 11, 2021, 10:05 am
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Hello everyone,

I have strange problem when I tried to rerun error points. In my simulation, I got some points with "sim error", and I have checked output log, there was no error in it.

I tried to rerun these points, but virtuoso closed automatically when it reloaded the result. And I got "Segmentation fault (core dumped) " in linux terminal. I have large memory so memory should not be the problem. Then I updated the spectre simulator to 20.1.0.298.isr9(I used 19.10.541 previously), and ran the whole simulation again. I still got some unfinished points and virtuoso closed again when I reran....

My Virtuoso version is IC6.1.8-64b.500.14 and I'm running transient simulation with 40000 sweep points, and I'm using adexl..

Thanks a lot for help.

Regards,

Holz

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$finish_current_analysis in verilogA

August 11, 2021, 7:12 pm
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Hi,

I am using a verilogA block in my simulation and it includes the statement $finish_current_analysis to stop the simulation when the event I am interested in happens. It works correctly if I simulate a single run in the Explorer. However, if I try to run Monte-Carlo simulations (still from within the Explorer) it seems the simulations don't stop. All MC runs are listed as "running" in the results window of the Explorer. Interestingly, if I open the spectre.log file for any of the MC runs I can see there that the simulations have actually finished at the time the event has happened. Bottom line, since the MC runs don't really quit I can't get my expression results and the statistics for that.
Maybe I am missing something about the use of that $finish statement in the context of MC simulations. Suggestions are welcome.

Thanks

Svilen

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How to add variable in model files?

August 12, 2021, 3:57 am
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There is some perimeter in model file which I want to access as a variable and can easily edit from design variable option. Can you please help me on that about how to add variables in model file?

For eg:-

The above picture is small section of a model file. There is a parameter "k" which I want to access as a variable in Design Variable of ADE Explorer or anywhere else, so that I can easily sweep the parameter. Can you please help me on it?

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annotate text to a schematic from a file every time the schematic is opened or refreshed

August 12, 2021, 5:21 am
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Hi all,

This might be an oddball request but I'm going to ask it anyway.

I have a text file containing a simple text message, which, say indicates the health of a circuit. This would be something that I generated myself, or a simulation wrote out at its conclusion.

Ideally, I want the contents of the text file to appear in a schematic view when I open it or do a descend-read from the top-level. This is a bit like back annotation I guess, which I know nothing about, but I think I just want something which reads a file and puts the text in the schematic automatically without any simulation being run. The name of the file would be stored in the schematic view somehow. Is this possible?

Thanks for reading!

Derek

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Square pins on symbols in verilogin

August 12, 2021, 5:43 pm
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Hi

Really dumb and nit picky question - is there a way to make the symbols generated by verilogin use square pins rather than the longer rectangular pins?  I can't seem to find an option.  I'm using Virtuoso 6.1.8-64b.500.17

Thanks

Chris

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Noise Figure of track and hold circuit

August 13, 2021, 4:14 am
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Hi, I am trying to get Noise Figure in track and hold circuit with RC>>Ts/2. My ckt is like RC low pass filter {Port(with res=50) + switch + cap to gnd }

NF= 10logF,  where F is Noise Factor
and F = (Ni+Nsys)/Ni.

In my circuit Nsys = 0 (Sys include only switch and cap, there is no res(noise generator)). so, F should be =1, so the Noise figure should be = 0.
But, cadence giving me F = 1.96  and NF = 2.92 dB. (I am measuring it with Pss+Pnoise)


what I am doing wrong?

                              

                                              

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Using SystemC models in ADE

August 14, 2021, 9:51 am
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Hi,

Is there a way/documentation to use SystemC models in ADE-based simulations? I know the RAK about SystemVerilog in ADE-based AMS simulation. Is there a similar RAK about SystemC?

Thanks, Chris

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How to simulate a mixed-signal system if power-supply is time-varient

August 15, 2021, 9:26 pm
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Hi, I'm working on system verification using AMS. For one case, the power-supply VDD is changable during simulation.

I'm using connect_rule, and tried to modify vthi/vtlo but failed with some errors. Finally I wirte a levelshift.va to process the interface voltage,it works.

So, what is common method to process this simuation, thank you! 

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Library charecterization without post-layout netlists

August 16, 2021, 10:15 pm
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Hello.

I want to characterize cells created in Virtuoso into a standard cell library. I do not have access to the LVS and extraction tool that is supported by the PDK.
(The foundry's golden tool is Calibre/XRC and they do not generate PVS decks without a tapeout commitment. I only have access to assura and PVS.)

Is there a way by which I can characterize the cells without a post layout netlist?
Otherwise, is there a cloud-based service which I can use for this particular project?

Thanks in advance for taking time to answer this question :)

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Server processor selection - any difference in performance and features (AMD Epyc - Intel Xeon)

August 17, 2021, 6:25 am
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Hi all,

we are about to get a new server for our ASIC development.

We have to decide between AMD-Epyc-32cores (cheaper) and Intel-Xeon-24cores (more expensive).

We are wondering if there would be any performance difference and/or feature advantage when selection Intel over AMD (e.g. multi-threading, mutli-processing, etc.)

We are mainly doing analog simulations and layout (Virtuoso), but also digital simulations and synthesis.

Please share your experience, to help us find a proper decision.

Thx

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VIVA Evaluation error for calculator expression over corners in ADE Assembler

August 17, 2021, 10:37 am
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Hello,

I am using Cadence Virtuoso version IC6.1.8-64b.500.6

I have designed a frequency output temperature sensor. I have formulated the sensor sensitivity s(f) over corners, which is yet only the temperature, the basic idea is to monitor the sensitivity change with T which helps me to investigate the sensor linearity. 

I used the ADE assembler to enter the sensitivity expression, which simply df/dT, where I used the Cadence calculator to calculate it using the "deriv" function. I have selected "all" from the EvalType.

Until this point there is no problem, I run the simulation and cadence presented me correctly the sensitivity over corners as shown in the picture below:

Then later I wanted to do more calculation over it by sending it to the calculator, for example applying average or whatever function. The data type in the calculator looks like as shown below

And I recived the following error after applying my averag function to the signal as shown below

Thank you for your help in advance

Regards

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Update VerilogA outputs during simulation based on values read from from

August 17, 2021, 11:13 am
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For verification of an analog block, I am trying to set up my testbench such that I can change the output of a verilogA input stimulus during transient simulation. The goal is to read a text file at every rising edge of a clock and use the value to change the behaviour of the analog block. The text file will contain only a single line with a single integer value. The version of Spectre is 20.10.isr3

In Spectre X simulation log, I see the CSV file, PGA_GAIN_DATA, being read at the first crossing event with the message "Reading file: /home/c99485/simulation/sandbox/sandbox/maestro/results/maestro/PGA/netlist/PGA_GAIN_DATA.txt". the output bus of the verilogA was also updated. However, all subsequent crossing event did not yield any other messages and it appear that Spectre simulator would just reuse the data that it had acquire from the first read and stored in its memory. Removing or renaming the file after the first instance did not affect the transient simulation. 

Is this behaviour expecter? Can I get Spectre to re-read the CSV file and not reuse the data from its memory? 

==========

// VerilogA for sandbox02, CTRL_PGA, veriloga

`include "constants.vams"
`include "disciplines.vams"

module CTRL_PGA (VDD, VSS, PGA_GAIN, CLK);

  output [3:0] PGA_GAIN;
  inout VDD, VSS;
  input CLK;

  electrical [3:0] PGA_GAIN;
  electrical VDD, VSS, CLK;

  integer OVR_PGA_GAIN;
  integer fileID, retval;
  real vthres;
  genvar i;

  analog begin

      @(initial_step) begin
         vthres = V(VDD)-V(VSS);
         OVR_PGA_GAIN = 0;
      end

     @(cross(V(CLK) - vthres, 1.0)) begin
        fileID = $fopen("PGA_GAIN_DATA.txt", "r");
        if (fileID > 0) begin
          retval =1;
          while (retval == 1) begin
          retval = $fscanf(fileID, "%d", OVR_PGA_GAIN);
        end
      end
    end

    for (i=3; i>=0; i=i-1) begin
      V(PGA_GAIN[i]) <+ (OVR_PGA_GAIN>>i)&1 ? V(VDD) : V(VSS);
    end

  end
endmodule

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Simulation of gate leakage current using cadence

August 19, 2021, 6:59 am
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Hi, all

I'm going to test the gate leakage current in TSMC 180nm process.

I connect a DC voltage to the gate of an NMOS transistor, and do DC(and tran) simulation, the results of Ig is nan. I'd like to ask if I'm running the right simulation? Does tsmc 180nm support to test the gate leakage current? Do I need to set some parameters in cadence?

I'm looking forward to your reply|!!!

Best

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EMIR simulation fails with EMIR-1099 code

August 20, 2021, 2:17 am
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As shown in the picture, I don't understand what causes this

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