Quantcast
Channel: Cadence Custom IC Design Forum
Viewing all 4919 articles
Browse latest View live

Picking corner dependent variables for monte carlo simulation

$
0
0

I have two simulations:

1. Calibration sim - (used to obtain a 5 bit variable)

2. Actual sim - (uses 5 bit variable from calibration sim to check other transient conditions)

I run the first sim (calibration sim) across 7 corners (TT, FF, SS, FS, SF, SSAG, FFAG) and get a set of 5 trim bit variables calibrated according to the corner. The variable is called cal_code<4:0> (5 variables). 

Now I want to run a process+mismatch 500 point monte carlo (global + local) on the second sim (actual sim) using the info from the calibration sim in such a way that it picks the right set of 5 bits for the corresponding corner in each iteration of the monte carlo sim. 

Essentially this is similar to what would happen in real life silicon. A single wafer would first be calibrated to obtain a correct 5 bit setting and then the calibrated setting would be used to test all further things for that chip. So in analogy, each individual chip that is manufactured can be considered a single iteration of the monte carlo.

Any ideas on how to do this?

community.cadence.com/.../monte-carlo-on-a-verilog-a-custom-macro-model-based-on-device-instance-not-subckt-instance

This would have been helpful if I was just doing corner runs and not monte carlo.


Layout xl highlight dimming vs selecting

$
0
0

When using net highlighting option in Layout XL, the dimming option for other nets and layers is enabled. It acts as a shadow effect. It makes other objects darker.

I want to enable the same effect on the cyclic option between schematic and layout. For example, when selecting a device in the schematic, it is selected in the layout. I want the selected object in the layout to get this dimming effect. However, it is better to be enabled only if the devices selected from the schematic. Because, sometimes it is hard to spot the selected devices in the layout, so the dimming effect would help in this.

Is there something similar to the following command but for the cyclic selection between schematic and layout?

layout displaySelectionHighlightWhenDimmed boolean { t | nil }

Changing the height and width of a viva graph

$
0
0

Hello,

I would like to change the height and width of viva graph but It it doesn't seem to take effect after adding this in my .cdsinit

width
envSetVal("viva.graphFrame" "width" 'string "600")
; height
envSetVal("viva.graphFrame" "height" 'string "500")

I have also looked at these older posts:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/11245/how-to-set-a-size-for-the-waveform-window-while-using-ocean


https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/30504/setting-up-used-defined-graph-properties

How can I change the height and the width of the wave graph? I also went into the graph property and changed the analog height and analog width but it is not changing the height and width.

My cadence virtuoso version is :
Version IC6.1.8-64b.500.9
Spectre spectre191

Thank you very much for your help.

Corrupted GUI display

lxCheckAgainstSource() command query

$
0
0

Hi Andrew, 

I am using ICADV18.1 ISR10 and I have a query related to lxCheckAgainstSource command.

lxCheckAgainstSource(d_schCellViewID
d_layCellViewID[ ?masterDiff { t | nil }] [ ?paramDiff { t | nil } ] [ ?unboundInsts { t | nil } ] [ ?connectivity { t | nil } ] [ ?maxDiffsLimit x_maxDiffsLimit ] [ ?logFileName t_logFileName ] [ ?appendToLog { t | nil } ] [ ?nameDiff { t | nil } ] [ ?dummyDiff { t | nil } ] [ ?busTermDiff { t | nil } ] [ ?virtualHierDiff { t | nil } ] ) = t / nil



  

The command has almost all options in the form, except "Open workspace", (highlighted in red in the above picture)

The "Open workspace" option in the form opens "CAS" workspace and enables the CAS tab in the Annotation Browser, as shown below:



I can se the CAS workspace using the following command
deSetWorkspace(geGetEditCellViewWindow(cv) "CAS")

But I cannot enable the CAS tab in the Annotation Browser. How can I enable the "CAS" tab in the annotation browser, after running lxCheckAgainstSource command?

How to make Display Option automatically loaded for layout

$
0
0

Is it possible to make Display Option automatically loaded for layout whenever I open a file for layout?
Now I have to set it each time and sometimes I forgot so off gird error happened.
I have a file including setting but don't know how to make it load automatically.

(IC6.1.8-64b.500.8)


group and ungroup in layout L

$
0
0

Is it possible to temporarily group some components together for alignment all of them at the same time and then ungroup after alignment in layout L?
(IC6.1.8-64b.500.8)

Turn off i/f noise in Transient Noise simulation

$
0
0

Hi everyone,

I got a question here: how could I turn off the flicker(1/f) noise of a circuit in Transient Noise simulation? 

Please let me know if you have any clue! Thanks a lot!

Best,

Jessica


ADE Explorer - Simulation job was suspended - Corrupted the results .rdb

$
0
0

I have a setup, where an external script will suspend low priority simulation runs, from time to time, based on license requirement within our team.

Often this works as a charm. But sometimes, a suspended run shows up as 'running' or 'sim err', even though the simulation has finished. See atttached screen shots from the ADE and the logfiles from the same runs.

All the data is available in the result folder, with all the psf seemingly correct (waveform data can be plotted from the Results Browser). However, I cannot perform any calculations on this database, and all my calculation are reported as 'sim err' or 'running'. Clicking the Update Results, doesn't do anything, pointing to the results of Explorer.0, using Results -> Select... doesn't help either.

Firstly, what has most likely happend in this case? Is the .rdb file within the maestro view corrupted, or is there some other explanations?

Secondly, is there a way to perform 'new' calculations on the resulting PSF, or somehow make the ADE perform the calculations correctly?

Br,

Christian

Versions:

Virtuoso IC6.1.8-64b.500.12

Spectre 19.1, running aps++

Custom Grid Creation According to .tlef

$
0
0

Hello,

I am inquiring about how to create a custom grid according to the .tlef metal routing tracks. The problem I seem to be running into is that Virtuoso only allows you to create a rectangular grid, however most routing tracks of the first two metal layers are offset so as to create a rectangle (removes parallel plate capacitors when routing is performed in non preferred direction). I have been reading the Virtuoso Layout XL documentation and the only thing I could find was the Display -> Grid Settings area in which you can set Minor and Major spacing, however regardless of how you do this it performs the spacing in both the x and y directions, therefore creating a square. However, I really am in need for a rectangular grid shape. Does anyone have any insight on this? A lot of other tools, such as Magic, allow this functionality, therefore I assume Cadence does too I am just missing something.

Thanks in advance!

How to include an Instantiated Verilog cell in the config view of AMS simulation

$
0
0

Dear All,

I have created a VerilogAMSTEXT  module called sync_block.

The module text looks like bleow :-

It has two instances sync_a ad sync_b. These are defined in separate files sync_a.v and sync_b.v.

Though these files are included in the Text, the config is NOT able to detect these cells.

Could anybody please tell how this issue can be overcome.

`include "constants.vams"
`include "disciplines.vams"
`include "/test/sync_a.v"
`include "/test/sync_b.v"

module sync_block #(parameter RESET_TOGGLE_LEVEL = 'b0)

(
input async_toggle_i,
input clk_i,
output pulse_o,
output toggle_delay_o
);

wire toggle_sync;

sync_a #(.RESET_LEVEL(RESET_TOGGLE_LEVEL)) i_sync (
.d_i (async_toggle_i),
.clk_i (clk_i),
.hw_reset_n_i (hw_reset_n_i),
.sw_reset_i (sw_reset_i),
.test_mode_i (test_mode_i),
.z_o (toggle_sync)
);

sync_b #(.RESET_TOGGLE_LEVEL(RESET_TOGGLE_LEVEL)) i_toggle2pulse (
.clk_i (clk_i),
.hw_reset_n_i (hw_reset_n_i),
.sw_reset_i (sw_reset_i),
.toggle_i (toggle_sync),
.pulse_o (pulse_o),
.toggle_delay_o (toggle_delay_o)
);

endmodule

ERROR in AMS simulation : "expecting a valid compiler directive [16(IEEE)]"

$
0
0

Dear All,

I have a verilog code portion as below:-

But, when I run I get error as :- ncvlog: *E,EXPCPD ... expecting a valid compiler directive [16(IEEE)]. `#if $NUM_STAGES$ > 2.

Could any body please tell how to fix this issue.

`#if $NUM_STAGES$ > 2
sync_mod i_sync_cell(
.Q(z_o),
.CD(~reset_n_i),
.CP(clk_i),
.D(d_i_sg2),
.SE(1'b0),
.SI(d_i_sg2)
);
`#endif

ADEXL different accuracy setting for sub-blocks

$
0
0

Hi,

I'm doing a large post-layout circuit transient simulation. I only need high accuracy on part of the entire circuit. Using "conservative" will be applied to the entire netlist and it will slow down the simulation. Is there a way to only specify some transistors to be "conservative", while the rest to be "liberal"?

Thanks,

-Tao

Generating schematic using pin information from layout

$
0
0

Hi All,

I have an IC layout and it's pin information. I need to create a pin only schematic for this layout. The no of pins are more than 150 so is there a way to create this pin only schematic apart from manually placing one pin at a time ?

thanks

How to run the routine CCSputOnGrid.il?

$
0
0

I'm trying to run the code for correcting offgrid error here.
The first step is :

a. Load the SKILL procedure via .cdsinit file/CIW

  load("CCSputOnGrid.il")

I did that but got the error *Error* load: can't access file - "CCSputOnGrid.il".
I think the code should be put in some folder?



use of PTM 16nm finfet models for simulation

$
0
0

Hello everyone,

im new to spctre simulation on cadence, my project involves a circuit desgin and simulation based on FinFET devices. I have downloaded the FreePDK15 files and PTM 16nm models from the respective websites.

I referred to this site http://venividiwiki.ee.virginia.edu/mediawiki/index.php/FinFET_FreePDK15_Tutorial#Use_FreePDK15_with_Cadence for help, but i am unable to understand what parameters i must add in the cdf list.

if anyone could guide me through this, i would be greatful.

thank you.

Calibre / PEX / During Calibre view creation / *Error* close: argument #1 should be an I/O port (type template = "p") - nil

$
0
0

When I run PEX (passes LVS) and try to create a Calibre view, it goes through "Running Back Annotation Flow", then it errors out:

Calibre View generation encountered a fatal Error.
Please consult the logfile for messages.

The only error message from the log I can see is this:

*Error* close: argument #1 should be an I/O port (type template = "p") - nil

I have been digging forums, etc. but cannot seem to find what is wrong with this PEX.

What is argument #1 and type template "p" anyways?

Thanks,

Sunwoo

PS I am using "sub-version IC6.1.8-64b.500.6 "

Ideal ADC model setting in adhllib

$
0
0

   

Hi everyone,

Does anyone know how should I set an ideal ADC in adhllib? Specifically parameters "Vref" and "model".

And a general question; I remember in ADS tools by clicking on "Help" we would be directed to a page to see how to set the parameters of a specific component. Is there such option for Cadence? (when I click on help it direct me to a page, but nothing is said about that component setting)

Thanks

Mostafa

SKILL: How to have multiple schematics open and modify the instance properties in them without closing the schematics

$
0
0

My situation is I need to copy the instance property from one schematic to another one. For example, I have schematic_source and schematic_target. The instances in schematic_target is a subset of schematic_source.

For example, schematic_source has C0-C99. schematic_target has C0-C9. I need to copy the width and length property from source to targer for C0-C9.

It seems that I am encounting an issue that I cannot select the schematic I want: The ddsServOpen command automatically select the new opened schematic. So, when I first open the source and target schematics, the selected schematic is the one that is opened latter. And when I loop through C0-C9, there is no way for me to tell the tool to select the source schematic and query the property there.

Below is my pseudo code: 

ddsServOpen(schematic_source )
ddsServOpen(schematic_target )

source_cvId = dbOpenCellViewByType( schematic_source )
target_cvId = dbOpenCellViewByType( schematic_target )

instances_target= target_cvId->instances;

foreach( instance instances_target

instance_name=instance~>name
printf("instance name is: %s\n",instance_name)
refObj_source = rodGetObj( instance_name source_cvId)
instance_dbId_source = refObj_source~>dbId
;get the values {w,l,connection,segments} FROM source
geDeselectAll()
geSelectObject( instance_dbId_source )
schHiObjectProperty()
w=schObjPropForm->w->value;
printf("w=%s \n",w)
l=schObjPropForm->l->value;
printf("l=%s \n",l)
hiFormDone(schObjPropForm)
geDeselectAll()
; put the values {w,l,connection,segments} TO target
refObj_target = rodGetObj( instance_name target_cvId)
instance_dbId_target = refObj_target~>dbId
geDeselectAll()
geSelectObject( instance_dbId_target )
schHiObjectProperty()
schObjPropForm->w->value=w
schObjPropForm->l->value=l
hiFormDone(schObjPropForm)
geDeselectAll()

);end foreach

It seems that when the first schHiObjectProperty() is executed. The tools has the target schematic selected. So, although the instance in the source schematic is selected as I can see it, the "q" button is applied on the target schematic, and therefore, will not pop up the property window of the instance from the source schematic, and therefore, the w and l is nil in the first place.

The non-elegant solution is probably is probably I open and close the schematic on the fly, each time having only one opened schematic. But I fear that it creates too much overhead in opening and closing. I wonder whether is a more timing efficient to tell the tool that I want to select one of the two windows that are open, by name or ID.

 

ADE Assembler evaulates expression prior to simulating - long wait

$
0
0

Hi,

Based on feedback from Andrew Beckett, in another thread, I recently moved a simulation setup to the LSCS job control mode, instead of ICRP.  Now, every time I launch I get a ton of errors printed in the CIW, along the line of ERROR (ASSEMBLER-2709): Evaluation returned 'nil'.

Since I have a significant amount of errors here, it takes quite some time, before all these errors are printed, and the simulation even starts (half the time from I press simulate, to it finishes, is at least this waiting for this). When the simulations are done, none of these errors are actually true errors.

It seems most likely that LSCS calls some expression evaluation, prior to launching a simulation, evaluating none-existing expressions and then waits until this is done.

Can this behaviour be modified or circumvented? I've looked in the user guide, to no vail.

Versions: Virtuso 6.1.8-ISR14, Spectre 20.1.base

Br,

Christian

Viewing all 4919 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>