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Cell Abutment Wiring Warning !
Hi,I am using Virtuoso XL for my layout. The abutment sever as well as auto abutment are enabled in it. When I abut the existing Pcells, let's say 2 PMOS devices like below, abutment works just fine....
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Cadence Liberate Characterization of Complex Logic Cells
Hi,I am trying to characterize a combinatorial circuit which has 5 (A, B, ...., E) inputs and 3 outputs (X, Y, Z). As per the cell behavior, output Z does not depend on input E. When I perform the...
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COmmand to find Process Name
Hi,Is there any command in cadence skill to find the process name Like if it is tsmcn28rf or other proces nodesPlease let me knowThanks,Nirmal.
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how to find input impedance of common gate configuration
what is the general way to find input impedance of common gate amplifier stage. I tried to provide input as IAC mag =1 , trying to find the impedance at input node (Vin), trying to make it as(Vin/In)...
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QRC Assura Extraction failing !
Hi I'm trying to run parasitic extraction on Assura QRC, and the run is failing. The log file says that it couldn't get the library models for the NMOS, PMOS. Something like this:My setup is as...
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Placing of physical design into another physical design in innovus
I want to place physical design of memory macros that I have created separately in another main design in innovus..How to do that??
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Layout editor: quick align "Move/Stretch" mode deprecated in ICADV?
Hi! The "Move/Stretch" mode is not available in my layout editor (L) in ICADV 12.3. Here's a comparison of what I see in IC 6.1.6 (28nm PDK, left) and ICADV 12.3 (16nm PDK, right):Moreover, the Layout...
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tran statement in spectre
I have used the below commands for tran statement for 1000 point tran1 tran stop=4e-8 strobeperiod=4e-11tran1 tran start=0 stop=4e-8 strobeperiod=4e-11but strange, in all print file i am able to view...
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Plot RMS noise over time with AMS simulator
Hello everyone,I have a delay element made of a current source (pMOS) + capacitor towards GND. I would like to plot the RMS noise on the capacitor over time, after running a AMS simulation I know it...
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spectre +aps simulation: the vsources devices with dc=0 are removed, so the...
Hi there,I have next situation: in some schematics are some vsource(s) used just as nets separators or to probe the currents. In most of the cases type=dc.They are preferred by designers versus iprobe,...
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vsource parameters cleared when changing source type
Hello,I am experiencing an issue with the vsource from analogLib. If I change the source type then then all the previously entered parameters in the form are cleared. I am remembering from past...
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schematic search/replace criteria combination
Hi guys, I am trying to do such replacement in schematic hierarchy: change all libName_A/cellName_A to libName_B/cellName_A, which means I need to combine libName and cellName together when I do...
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Monte Carlo analysis on schematic Vs post layout
Hi,Is it more appropriate to run Monte Carlo simulation on circuit schematic or on the post-layout extracted version?Will the mismatches be captured more realistically if the analysis is run on the...
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OCEAN: How to Check if a Corner is Enabled/Disabled?
Hi,It is well described on the manual how to enable/disable corners. However I could not find a way to check when a corners is indeed enabled or disabled - since all corners are returned from...
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Stability and transient analysis do not match
Hi all,I'm using virtuoso subversion IC6.1.7-64b.500.21 and spectre subversion 18.1.0.143.isr1.I'm verifying stability in a nested multiloop LDO design, so I've introduced several probes to analyze...
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bindkey to display Assembler/ADE XL->options->save
Hi All, Is there anyway to define a bindkey to activate the pop-up window of Assembler/ADE XL->options->save? Thanks for your help!BR
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per-test config variables in ADE XL
I have two different blocks whose active view I need to vary in different ways and I'm hoping to find some guidance in the best way to do it. The first is an opamp in the circuit being tested. I want...
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include file in subckt in ADE .
My end goal is to get a netlist I don't need to touch. Is it possible to create an schematic_RCX view for a cell (regular schematic view) and add a component to that schematic which specifies a file to...
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Cannot select a layer. Layer-Purpose pair does not exist in LSW?
Here is my problem. I've added an instance of a low-leakage nmos in the layout editor using 'Add Instance' menu. Now, that instance makes use of a layer called 'CPH'. However, the layer is written in...
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Cannot run Assura RCX
Hello,I am trying to do a post-layout simulation of a ring oscillator to determine why there is a discrepancy between the simulated oscillation frequency and the fabricated chip. Unfortunately when...
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