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Error in layout extraction
Hi, I am trying to check the DRC for my layout design, when I run DRC I got this error with the following message:sh: -c: line 0: syntax error near unexpected token `('sh: -c: line 0: `cp...
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Is there the ability to check in an ADE Assembler license outside of the...
Hi,I am using SKILL code to do netlist generation outside of the ADE gui. I do the following:envSetVal( "spectre.envOpts" "setTopLevelAsSubckt" `boolean t) envSetVal( "spectre.envOpts" "switchViewList"...
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VIVA-XL – How to differentiate same signal waves from different db’s
Hi,I am running Cadence version ICADV 12.3-64b.8When I open multiple db’s based on similar testbench (Example: same I/O, Stim etc. but use netlists with different sized devices) and plot a signal from...
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License Mistake
Dear all.Today, when I run my file in Virtuoso, the dialog appeared: (icLic-23) License Virtuoso_Layout_Suite_L ("95300") is not available to run Layout-L. Would you like to try checking out the...
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Schematic Pcell : internal node probing
Hi,Is it possible to probe internal nodes for a stacked Schematic pCell.I have a stack config where multiple transistors are stacked and want to probe internal node.When I try this through normal...
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Retaining Pcell and Via Library Reference while Streaming in the GDS
Hi All,How do i retain the Pcell properties while streaming in the gds which was streamed out turning the flatten Pcell switch off.Is there a switch which can be turned on while streaming out or...
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Computer specifications for Cadence Virtuoso
I am going to buy a new PC for running Cadence Virtuoso. The simulations that I will be working with would be DC, AC, PSS, Noise, and Transient (Specifically because I might need to run these in...
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running aging simulation with different bias voltage and temp over time
Hi,Is it possible to run aging simulation for two pattern, say we we want to run aging sim for 10 years, for first 5 years VDD=1.8V & temp=30 and next 5 years it should be VDD=3V and temp=45.I...
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Voltus-Fi Peak static current analysis treatment of decoupling caps and...
Hi,I have a couple of questions regarding how Voltus-FI static IR-drop analysis:1. How does it treat decoupling caps and dummy or inactive transistors (Pmos with VDD-connected gates, Nmos with grounded...
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hierarchy info for each fet in the design
Hi,I need ful hierarchy for all the fet in the design. A flat netlist is the easiest way to go but spectre does not has a way to get any flat netlist. So the only option is to get it from some SKILL...
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PSS shooting with s-parameter file
Hi,When I have a s-parameter file in the circuit, PSS will report error and suggest to use hb engine. I wonder if there is a way to include s-parameter file and keep shooting engine in pss.It says I...
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regarding layout netlist
Hi all,I am searching an option to export only netlist for layout in icfb.Somebody please help me.Thanks,Ganesh Doddipatla.
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How to check to see if we have Voltus license >
HI ,Does anyone know how to check our env to see if we have Voltus license? thanks Nhumai
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PSS shows inaccurate output results when no convergence reached
Hi,I have another question on PSS simulator with hb engine.I am simulating a circuit that settles after a certain time. If the circuit does not settle properly, for instance, ends up with an unwanted...
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LVS issues with Hierarchy
Hi All, I have big Analog, small digital block. Most of my design is custom based Analog, done with Virtuoso Schematic and Layout. the small digital blocks, i did digital flow, exported gds and...
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error in checking lvs test with calibre tool in cadence ic
hi i'm trying to apply lvs test to the layout of my circuit that is a transimpedance amplifier which uses 4 spiral inductors .the problem is when i try to check lvs it gives me the following errors :no...
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Reduce the spacing between metals while placing stack auto via.
Hi,While placing Auto via from M4(H) to M6(H) and there are some M5(V) routing on them it will add via where M5 is not there and will keep spacing between M5s those are routing and M5 in via.It is...
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NPORT file path
Dear Community,I wonder if I can set the S-parameter data file path parameter in the schematic as variable and sweep it among discrete values.Sample scenario: Some data link has an input power...
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Plot noise voltages for more than one node
Doing noise simulations, it seems that I can only select one single node to plot the resulting noise voltage.Selecting multiple nodes seem not to be provided - right ?I want to plot the noise voltage...
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How to recognise .GLOBAL statements from CDL models within AMS
Hello,I am running a mixed signal simulation where my standard cell instances are defined using a .cdl model file which contains information like this..subckt adc12_stdcell_ADDFHX4 CO S A B CIM0 net76...
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