Adapt .cal file to .rul file for PVS
Hello there,So I have been working with a specific PDK for Cadence designing and simulating analog circuits with Virtuoso and ADE. When doing the physical layout however, the files provided for the...
View ArticleHow to inquire the discipline of a specific net in an AMS simulation via...
I am using $cgav in a systemVerilog test to get a voltage from and electrical node in an AMS simulation.The AMS simulation in based on a HED config that could have a specific block either as a...
View ArticleVSR: How to avoid router to route over floating fill
Hi,I am trying to resolve an issue where router is routing a metal layer directly on top of a floating fill layer of the same layer. Are there any constraints to set to avoid this. This is causing a...
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Fetching the operating point of a transistor in VerilogA with "$simprobe"...
I have the following schematic:"VerilogA_Test" block is written so that it takes the transconductance gm of the transistor MN0 and prints its value.The VerilogA code is the following:`include...
View ArticlePlotting Template in ADE Assembler and ADE Explorer
My virtuoso verison is: sub-version IC6.1.8-64b.500.27 I created two ADE Explorer cases and for each of them I saved a Plotting Template named differently such that no Plotting Template naming...
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Snap grid setup
Hi All,I would like to setup grids, Right I don't see any snap pattern option on grids palette. This is how I want I am using cadence 6.1.8 version. please let me know how do I setup these grids....
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Allegro Constraint Manager - Array
Hello,I have a reference design from TI. When I looked at PCB's constraint manager for Spacing, I found there are array of values separated by colon in each section. What is the meaning of these...
View ArticleTransient Noise Analysis (fmin)
Hello,I try to set the fmin via Tran Noise Options to 1Hz. However, fmin is limited to 1/simulationTime no matter what I set. First of all, if I run AC noise analysis, I know that within the frequency...
View ArticleSkill Pcell "undefined function pow" at eval during LVS
Hello,I've been working on a PCell in skill for several days and it is not a piece of cake! I was able to fix most of my problems alone, but this time I really don't understand...For a little of...
View ArticleIs spc file available in ADE Explorer/Assembler?
Hello,I am using an internal simulator as a shell around spectre and the input I have to give at least in older versions of Virtuoso was a .spc file. This was done by loading the ADE-L state, it would...
View ArticleRefer to output expression by name, when name contains whitespaces and...
Dear all,IC6.1.4 and especially Virtuoso Studio 23.1 allows to name output expressions in ADE and then used those named output expressions in other expressions by simply using its name (reference by...
View ArticleDifference srrWave and drWave
Going through the OCEAN Reference Manual the ocnPrint function mentions drWave as the waveform identifier. Checking the identifier of the results of my simulation, I get srrWave. What is the difference...
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Load Pull simulations without PortAdapter
HiI would like to run load pull simulations with harmonic balance analysis. I do not have access to PortAdapter from rfExamples library. So I would like to run it using analoglib port with hb analyses....
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Auto placer not updating PR boundary
Hi All, Could you take a look at the figure? I am trying to make the PR boundary on the left layout more compact and similar to the right. It seems the auto placer can do it, but sometimes it...
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LVS Mismatch
Hello,I added an LVS-cleaned design block at the top level with other blocks and components. At the top level, it is claiming again mismatched instances of the previously LVS cleaned block.It's a 130nm...
View ArticleVirtuoso IC6.1.8-64b.500.31 Crashing
After running several heavy simulations through ADE Assembler, the Virtuoso tool occasionally crashes, displaying the "Fatal Application Error". The design is quite large, at about 3GB, so the...
View ArticleMaestro - design variables form fetching deleted variables
I'm not sure how & why design variables is still fetching old variables which are deleted & replaced with values. Simulation will run fine but, when I click 'copy from cellview', old variables...
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"Ignore Instances" not completely ignoring capacitor instance effects
I'm simulating a CS-DAC, and was experimenting with the effect of an extra capacitor on the tail node. To do that, I placed an ideal cap from analogLib on the node, and then measured in three cases:No...
View ArticleocnPrint to File
Using `ocnPrint` to write a waveform to a file, I am unable to locate the file it writes to if it even writes to the file. I have tried relative and absolute paths and searched through the simulation...
View ArticleHow to use device models with spectre circuit simulator
Hi,I'm trying to use HiSIM2 with ADE-L.I read "Spectre Circuit Simulator Components and Device Models Reference". I believe the model is supported by cadence.However, I got the error below when I ran...
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