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[SOI device]How to deal with the backgate pin (VBGP & VBGN) settings of...
Hi, I got some questions.How to deal with the backgate pin (VBGP & VBGN) settings of devices with 5 terminals while running liberate?Q1: Is it correct to set the backgate an input pin while using...
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accepting 1st subckt definition when there are duplicate subckts
How can I make spectre accept the 1st subckt definition when there are duplicate subckts.Thank you
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AC Sim Output Setup Issues
Hi,I have the following setup defined in my outputs.After the simulation, I can see the "AC CL Gain" but nothing is seen for "AC CL Gain at 10kHz".Both the outputs are shown as plots. Any comments on...
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skip=cut inst=[...] statements being ignored
The following skip statement (included via "definitions file") works fine :- myScopedOpts options skip=cut inst=[i10.i0*] But it does not work when I try to use this:- myScopedOpts options...
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Spectre gives different DC simulation results for the same circuit (even some...
When I simulated the same two-stage op amp circuit in spectre many times, spectre gave different dc operating point simulation results (the following three pictures are the dc operating point...
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circuit prospector not finding structure
Hi All. I'm trying to use the Circuit Prospector in tsmcN12, but its not finding any structures like current mirrors or diff pairs. Is there something I need to configure like m-factor or...
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Printing out unconventional process-specific model parameter in ADE
Hi,Let's say you are performing a simple DC simulation of an inverter with 2 transistors in ADE. Is there anyway you can print out certain model parameters in the Spectre's output log file which are...
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Virtuoso Error
Hi All,I am trying to integrate "IC618" with a180nm standard PDK. When I am tying to launch Cadence with the command "virtuoso &" it is giving this...
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DC Annotation works sometimes and does not other times
In ADEXL, when back annotating to a schematic the node voltages don't always show up. I thought going through the list of libraries in Views->Annotations->Setup and setting them correctly seemed...
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DRC Error Using Assura
Dear Andrew,I am using "ICADVM18" version for virtuoso and "4.1_USR6" version for Assura for a standard 180 nm process. But when I am performing DRC, I am getting the some DRC errors. I have attached...
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Are there any rules and techniques for setting the accuracy and step length...
I built a two-stage op amp in the spectre and deliberately did not add a compensation capacitor.Then I connected this op amp into a unity gain negative feedback form, as shown in the figure below:I...
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Print Noise summary and corresponding OCEAN noiseSummary
Hi,the print/noise summary function available from ADE-L menu allows for hierarchical grouping of contributors, which is quite an handy feature.I don't seem to find a programmatic way to obtain the...
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global pins
I have many global pins(VDD! and VSS!). I f I connect them with metal, resistance increase. I want to connect global pins without physical in layout. Can I connect them in pex extraction and LVS.
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Can the stb simulation in Spectre calculate the negative phase margin?
When I was simulating a two-stage op amp, I tried to use stb to simulate its stability. At first I did not add a compensation capacitor (later I used ac simulation and the calculator to find that the...
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How to point to a CDL netlist in my config view
Hello,I have a CDL netlist of a digital block. That block is part of a larger hierarchy, rest of which is analog. So far I have been simulating with a model for the digital, and I point to it in the...
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Parasitic extraction tools for Cadence
Hi Andrew,I am using "IC6.1.8-64b.500.21" for Virtuoso and "4.1_USR6_HF11" for Assura. By using Assura I am able to do DRC and LVS check properly. However, I came to know that the RCX option is no...
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DC operating point for different analyses
Hello,I run several different analyses, i.e., ac, noise and dc, during a Spectre simulation. It seems that the simulator determines the DC operating point separately for each analysis. So, two...
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how to add printf statement to .cdsenv file?
Is there a way to put a printf statement in a .cdsenv file? Thanks
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Stimulating an internal node from a higher hierarchy level
Hi all.I'm creating a test bench for an APS matrix. Due to my diode voltages won't be measured or controlled, I haven't defined them as pins in my DUT. However, I would like to generate stimuli from my...
View ArticlePLL reference model for PSS+PNOISE
I am looking for a simple PLL reference model or design with mostly ideal components and adjustable parameters such as Kvco, Kpfd, LFP and reference/VCO phase-noise - which can be used in PSS+PNOISE...
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