Clik here to view.
Please ignore
Please ignore this. Dont know how to take a back a submitted question.Thanks!
View ArticleClik here to view.
Dynamic HZ node check issue
Hi,I have run the dynamic HZ node check, i got the list in the Check/Asserts in the results window. The history item is Interactive.0.But when i rename the Interactive.0 to XXX, the check result list...
View ArticleClik here to view.
Best way out of 2 ways to generate random voltage source (DC)?
Assume that I have a circuit with 4 transistors (with mismatch enabled) and therefore 4 digital inputs, and 1 digital output. I want to run transient simulation multiple times with Monte-Carlo mismatch...
View ArticleClik here to view.
2 Tone VerilogA signal source does not work in Harmonic balance
Hi all,I have a problem to get a Verilog-A signal source with two output tones to work in harmonic balance. So far my code looks more or less like this (deleted some calculations):// VerilogA for...
View ArticleClik here to view.
Trying to make a custom bindkey for Virtuoso to work - Select by line but for...
Hi Cadence Support,I am trying to create a custom bindkey for VXL that will do the following 1. Enable Select by Line, then 2. Disable selection for all object type except: via, pin, label,...
View ArticleClik here to view.
How to plot using Simulation files stored in a folder?
Hello,I have performed parametric simulation of 16000 points for a particular circuit and all the simulation files have been stored in the simulation folder. Can I plot graphs for these without running...
View ArticleClik here to view.
lxSeriesTerms for a 4-port device
Hello,I have a layout cell, where I want to expand a single schematic instance with the 's' property into several layout instances in series. However, the cell has 4 pins (p1 p2 p3 p4), with 2 pairs...
View ArticleClik here to view.
passing a result from previous test ADEXL
Hi Cadence Support,Trimming an oscillator or a bias or something similar , I need to find the right trimming code at the first test and pass it to the second.if your first test is named "DC_AC" , your...
View ArticleClik here to view.
pstb analysis shows different results at different iprobe position
Hi all, I tried to do pstb analysis for a voltage regulator with ping-pong autozero amplifier. However, I got different loop gain results when I place the iprobe at different node 1 and 2. the...
View ArticleClik here to view.
Generating data in csv format from netlist simulation
Hi All,is there a way to include commands in the netlist that dump out waveform results in a standard format like csv , txt or excel ?It will also be nice to know netlist statements to get the node...
View ArticleClik here to view.
How to flatten GDS by stream out or Command
Hi,I used follow skill but db not flattenprocedure( flatten( lib cell view)let((cvId)foreach(via cvId~>vias dbFlattenInst(via 32 t nil nil nil t nil t))foreach(inst cvId~>instance...
View ArticleClik here to view.
Verilog-ams fscanf EOF
I'd like to create a verilog-ams model. It needs read data from a text file with $fscanf command. After the last line of the file is read, a signal will given. How to detect EOF when read a file with...
View ArticleClik here to view.
Sort function to sort the paths selected using the bbox or beginpt or end pt
Hi Everyone.I am writing a code to join two bus kines i.e horizontal and vertical.I'm not able to find a way to to sort the path list with the bBox or Begin Pt oor End Pt. sometime teh selected order...
View ArticleClik here to view.
Transient stop time for specified number of clocks
Hello,I am optimizing a variable clock signal generator circuit by changing the circuit parameters in Cadence Virtuoso. I am running the transient simulation and calculating the generated signal...
View ArticleClik here to view.
Simulating with a Calibre Extracted Netlist with ADE Explorer
Hi,Need to simulate using an extracted RC netlist generated with Calibre. In the past I've used the Hierarchy Editor to generate a config view, point to the extracted "calibre" view, and simulate with...
View ArticleClik here to view.
Environment variable questions
Hi Andrew,I am using virtuoso IC618-64b.500.10. And i would like to set two environment variable as1. Schmatic/View/Net highlighting2. LayoutXL/Tools/Express Pcell Manager/ Enable express pcellsThanks...
View ArticleClik here to view.
About User Command-Line Options in Environment Options
Hi all,I'd like to know how to input several commands into the "User Command-Line Options" box.For example, +dcopt and +postlayout... and more.(Explorer-->Setup-->Environment Options-->User...
View ArticleClik here to view.
ADE Assembler Message 1921 - When running multiple sweep points
Greetings everyone,I would like to ask for some help with an issue that I have been facing while running simulations on a single transistor circuit.The process of creating the circuit and setting up...
View ArticleClik here to view.
recognize paths with metal jumps using DIVA
I have some devices that should be connected through a single metal connection:Is there any easy way to detect that situation (right) using DIVA?
View ArticleClik here to view.
How much storage does a single simulation use?
Hello everyone,I need to run a huge simulation with nearly 230k points, is it possible to check & test how much storage does a single simulation ṕoint need? I am going to run a larger simulation,...
View Article