Requesting any reference to intelligent LVS issue debugging

Hi,

I am working on analog circuit design using Cadence Virtuoso. The layout Suite I use is version IC6.1.6-64b.500.8

I never had any formal training on layout design. In last two years, I gathered only hands on knowledge by experimenting a lot. However, in last few months I am struggling with LVS issues which I am still unable to solve. I am requesting for any intelligent reference where I can get some help regarding the same.

Regards,

Saikat Chatterjee