Hi,
I have convergence issues even if I run very simple inverter circuit with fdsoi 28nm technology. Here I paste the schematic. As you see I tried to generate VSS=0 myself but still I have problem. Meanwhile, I paste my netlist and all the errors and warnings here.
I can not understand why I have these errors. Thank you for your help.
NETLIST
// Generated for: spectre
// Generated on: Nov 26 13:56:39 2018
// Design library name: SRAM1_13_11_2018
// Design cell name: testbench_26_11_2018
// Design view name: schematic
simulator lang=spectre
global 0 vss! VDD!
include "models.scs"
include "/home/azamolss/28nm/setup_working_dir/corners.scs"
// Library name: SRAM1_13_11_2018
// Cell name: test_26_11_2018
// View name: schematic
subckt test_26_11_2018 INPUT OUTPUT vdd vss
P0 (OUTPUT INPUT vdd vdd) lvtpfet w=80n l=30n as=6.08f ad=6.08f ps=232n \
pd=232n nf=(1)*(1) sa=76n sb=76n sd=96n ptwell=0 par=1 sca=-1 \
scb=-1 scc=-1 pre_layout_local=-1 p_la=0 lpccnr=0 covpccnr=0 \
ngcon=1 wrxcnr=0 nsig_delvto_uo1=0 nsig_delvto_uo2=0 soa=1 swshe=0 \
swrg=1 mismatch=1 m=1 xpos=-1 ypos=-1 plorient=1 plsnf=0
N0 (OUTPUT INPUT vss vss) lvtnfet w=80n l=30n as=6.08f ad=6.08f ps=232n \
pd=232n nf=(1)*(1) sa=76n sb=76n sd=96n ptwell=0 par=1 sca=-1 \
scb=-1 scc=-1 pre_layout_local=-1 p_la=0 lpccnr=0 covpccnr=0 \
ngcon=1 wrxcnr=0 nsig_delvto_uo1=0 nsig_delvto_uo2=0 soa=1 swshe=0 \
swrg=1 mismatch=1 m=1 xpos=-1 ypos=-1 plorient=1 plsnf=0
ends test_26_11_2018
// End of subcircuit definition.
// Library name: SRAM1_13_11_2018
// Cell name: testbench_26_11_2018
// View name: schematic
I6 (net7 net2 VDD! vss!) test_26_11_2018
V0 (net7 0) vsource type=pulse val0=0 val1=1
C0 (net2 0) capacitor c=50f
V3 (0 vss!) vsource dc=0 type=dc
V4 (VDD! 0) vsource dc=1 type=dc
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
tran tran stop=20n errpreset=conservative write="spectre.ic" \
writefinal="spectre.fc" annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub subcktprobelvl=2
And here is the errors and warnings:
Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 13.1.1.117.isr8 64bit -- 19 Jun 2014
Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.
Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.
User: azamolss Host: venus.tele.ntnu.no HostID: F1814302 PID: 14215
Memory available: 132.6755 GB physical: 135.4257 GB
CPU Type: Intel(R) Xeon(R) CPU E5-2640 0 @ 2.50GHz
Processor PhysicalID CoreID Frequency Load
0 0 0 2499.9 2.2
1 1 0 2499.9 0.2
2 0 1 2499.9 2.3
3 1 1 2499.9 0.2
4 0 2 2499.9 0.2
5 1 2 2499.9 0.0
6 0 3 2499.9 0.1
7 1 3 2499.9 0.0
8 0 4 2499.9 0.0
9 1 4 2499.9 0.0
10 0 5 2499.9 0.3
11 1 5 2499.9 0.0
Simulating `input.scs' on venus.tele.ntnu.no at 2:08:01 PM, Mon Nov 26, 2018 (process id: 14215).
Current working directory: /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist
Environment variable:
SPECTRE_DEFAULTS=-I.
Command line:
/eda/tools/cadence/mmsim.13/tools/bin/spectre -64 input.scs \
+escchars +log ../psf/spectre.out -format psfxl -raw ../psf \
+lqtimeout 900 -maxw 5 -maxn 5
Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ...
Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /eda/tools/cadence/mmsim.13/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file: /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/input.scs
Reading link: /eda/tools/cadence/mmsim.13
Reading file: /eda/tools/cadence/mmsim.13.11.117/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file: /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/models.scs
Reading file: /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/setupCornersIncludeFile.scs
Reading file: /home/azamolss/28nm/setup_working_dir/simulation/testbench_26_11_2018/spectre/schematic/netlist/importNetlist.scs
Reading file: /home/azamolss/28nm/setup_working_dir/corners.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_beol.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_feol.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_fet.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_varactor.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_varind.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_cmim16acc.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/common_esd.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_2t8x_lb.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/soa.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_2t8x_lb_wo_via.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2t8x_lb.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2t8x_lb_wo_via.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2u2x_2t8x_lb.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_6u1x_2u2x_2t8x_lb_wo_via.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_1t8x_lb.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_5u1x_1t8x_lb_wo_via.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/driftotp.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cvar_eg.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/pnpv.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/npnv.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_lohq_5U1x_2T8x_LB.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_hq_5U1x_2T8x_LB.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_lohq_6U1x_2T8x_LB.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_hq_6U1x_2T8x_LB.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_lohq_6U1x_2U2x_2T8x_LB.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ind_hq_6U1x_2U2x_2T8x_LB.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmim16acc.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/matching.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rvt.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/eg.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsd.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/dsw.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/dsv.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsl.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsp.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lsv.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egncap.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egpcap.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rpolyp.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rpolyh.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rndiff.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rnwell.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/diode.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rmetal.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/eglvt.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/grhcdsti.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/grhcdgated.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/hcdgated.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/hcdsti.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/rvtnfetsb.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egnfetsb.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/sblkndres.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/sblkpdres.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/hlvt.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/dsx.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/egext.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/cmom_rf_custom.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/veriloga.scs
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODEGR.va
Reading link: /eda/tools/cadence/mmsim.13/tools.lnx86/spectre/etc/ahdl/constants.h
Reading file: /eda/tools/cadence/mmsim.13.11.117/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading link: /eda/tools/cadence/mmsim.13/tools.lnx86/spectre/etc/ahdl/disciplines.h
Reading file: /eda/tools/cadence/mmsim.13.11.117/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Warning from spectre during AHDL read-in.
WARNING (VACOMP-2266): "$stop;<<--? "
"/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODEGR.va", line 799: Cadence Verilog-A treats the $stop function as if it were a $finish. The $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.
WARNING (VACOMP-2266): "$stop;<<--? "
"/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODEGR.va", line 841: Cadence Verilog-A treats the $stop function as if it were a $finish. The $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.
WARNING (VACOMP-2266): "$stop;<<--? "
"/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODEGR.va", line 879: Cadence Verilog-A treats the $stop function as if it were a $finish. The $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODE.va
Warning from spectre during AHDL read-in.
WARNING (VACOMP-2266): "$stop;<<--? "
"/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/ESD_DIODE.va", line 678: Cadence Verilog-A treats the $stop function as if it were a $finish. The $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.
Reading file: /eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/esdlayer.va
Warning from spectre during AHDL read-in.
WARNING (VACOMP-2266): "$stop;<<--? "
"/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/esdlayer.va", line 330: Cadence Verilog-A treats the $stop function as if it were a $finish. The $finish function always behaves as though the message level value is 0, regardless of the value you specify: The simulator does not report simulation time, location, or statistics about memory and CPU time usage.
Further occurrences of this warning will be suppressed.
Time for NDB Parsing: CPU = 1.15183 s, elapsed = 1.32661 s.
Time accumulated: CPU = 1.20382 s, elapsed = 1.32663 s.
Peak resident memory used = 52.6 Mbytes.
Reading link: /eda/tools/cadence/mmsim.13/tools.lnx86/spectre/etc/ahdl/discipline.h
Warning from spectre in `lvtpfet':`I6.P0', in `test_26_11_2018':`I6', during hierarchy flattening.
WARNING (SFE-30): "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs" 1453: I6.P0.lvtpfet: `swclipchk' is not a valid parameter for an instance of `utsoi2'. Ignored.
WARNING (SFE-30): "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs" 1453: I6.P0.lvtpfet: `pscedll' is not a valid parameter for an instance of `utsoi2'. Ignored.
WARNING (SFE-30): "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs" 1453: I6.P0.lvtpfet: `pscedlw' is not a valid parameter for an instance of `utsoi2'. Ignored.
WARNING (SFE-30): "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs" 1453: I6.P0.lvtpfet: `pncew' is not a valid parameter for an instance of `utsoi2'. Ignored.
WARNING (SFE-30): "/eda/kits/stm/28nm_fdsoi_v2.9/PDK_STM_cmos28FDSOI_RF_6U1x_2T8x_LB/2.9-07/DATA/MODELS/SPECTRE/CORNERS/lvt.scs" 1453: I6.P0.lvtpfet: `stcfl' is not a valid parameter for an instance of `utsoi2'. Ignored.
Further occurrences of this warning will be suppressed.
Time for Elaboration: CPU = 142.978 ms, elapsed = 143.429 ms.
Time accumulated: CPU = 1.34779 s, elapsed = 1.47051 s.
Peak resident memory used = 57.5 Mbytes.
Time for EDB Visiting: CPU = 2 ms, elapsed = 2.48098 ms.
Time accumulated: CPU = 1.35079 s, elapsed = 1.47342 s.
Peak resident memory used = 57.8 Mbytes.
Loading /eda/tools/cadence/mmsim.13/tools.lnx86/spectre/lib/64bit/mdl/libSpectreEH_sh.so ...
Global user options:
reltol = 0.001
vabstol = 1e-06
iabstol = 1e-12
temp = 27
tnom = 25
scalem = 1
scale = 1
gmin = 1e-12
rforce = 1
maxnotes = 5
maxwarns = 5
digits = 5
cols = 80
pivrel = 0.001
sensfile = ../psf/sens.output
checklimitdest = psf
save = allpub
subcktprobelvl = 2
tnom = 25
scalem = 1
scale = 1
Circuit inventory:
nodes 6
iprobe 12
assert 56
capacitor 3
resistor 2
utsoi2 2
vsource 3
Analysis and control statement inventory:
dc 1
info 8
tran 1
Output statements:
.probe 0
.measure 0
save 1
Notice from spectre.
42 warnings suppressed.
Time for parsing: CPU = 245.962 ms, elapsed = 322.604 ms.
Time accumulated: CPU = 1.59676 s, elapsed = 1.79641 s.
Peak resident memory used = 66.1 Mbytes.
~~~~~~~~~~~~~~~~~~~~~~
Pre-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~
Warning from spectre.
WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format.
Notice from spectre during transient analysis `tran'.
No checklimit analysis defined for asserts. A default checklimit analysis 'SpectreChecklimitAnal' has been created with all asserts enabled.
The following asserts will be enabled for all subsequent analyses until the next checklimit analysis statement is found:
I6.P0.soa_1351 : ON
I6.P0.soa_1352 : ON
I6.P0.soa_1353 : ON
I6.P0.soa_1354 : ON
I6.P0.soa_1355 : ON
I6.P0.soa_1356 : ON
I6.P0.soa_1357 : ON
I6.P0.soa_1358 : ON
I6.P0.soa_1359 : ON
I6.P0.soa_1360 : ON
I6.P0.soa_1361 : ON
I6.P0.soa_1362 : ON
I6.P0.soa_1363 : ON
I6.P0.soa_1364 : ON
I6.P0.soa_1365 : ON
I6.P0.soa_1366 : ON
I6.P0.soa_1367 : ON
I6.P0.soa_1368 : ON
I6.P0.soa_1369 : ON
I6.P0.soa_1370 : ON
I6.P0.soa_1371 : ON
I6.P0.soa_1372 : ON
I6.P0.soa_1373 : ON
I6.P0.soa_1374 : ON
I6.P0.soa_1375 : ON
I6.P0.soa_1376 : ON
I6.P0.soa_1377 : ON
I6.P0.soa_1378 : ON
I6.N0.soa_1239 : ON
I6.N0.soa_1240 : ON
I6.N0.soa_1241 : ON
I6.N0.soa_1242 : ON
I6.N0.soa_1243 : ON
I6.N0.soa_1244 : ON
I6.N0.soa_1245 : ON
I6.N0.soa_1246 : ON
I6.N0.soa_1247 : ON
I6.N0.soa_1248 : ON
I6.N0.soa_1249 : ON
I6.N0.soa_1250 : ON
I6.N0.soa_1251 : ON
I6.N0.soa_1252 : ON
I6.N0.soa_1253 : ON
I6.N0.soa_1254 : ON
I6.N0.soa_1255 : ON
I6.N0.soa_1256 : ON
I6.N0.soa_1257 : ON
I6.N0.soa_1258 : ON
I6.N0.soa_1259 : ON
I6.N0.soa_1260 : ON
I6.N0.soa_1261 : ON
I6.N0.soa_1262 : ON
I6.N0.soa_1263 : ON
I6.N0.soa_1264 : ON
I6.N0.soa_1265 : ON
I6.N0.soa_1266 : ON
************************************************
Transient Analysis `tran': time = (0 s -> 20 ns)
************************************************
Trying `homotopy = gmin' for initial conditions.
Trying `homotopy = source' for initial conditions.
Trying `homotopy = dptran' for initial conditions..
Trying `homotopy = ptran' for initial conditions..
Trying `homotopy = arclength' for initial conditions.
None of the instantiated devices support arclength homotopy. Skipping.
Error found by spectre during IC analysis, during transient analysis `tran'.
ERROR (SPECTRE-16385): There were 7 attempts to find the DC solution. In some of those attempts, a signal exceeded the blowup limit of its quantity. The last signal that failed is I(V4:p) = 1.58867 GA, for which the quantity is `I' and the blowup limit is (1 GA). It is possible that the circuit has no DC solution. If you really want signals this large, set the `blowup' parameter of this quantity to a larger value.
ERROR (SPECTRE-16080): No DC solution found (no convergence).
The values for those nodes that did not converge on the last Newton iteration are given below. The manner in which the convergence criteria were not satisfied is also given.
Failed test: | Value | > RelTol*Ref + AbsTol
Top 10 Residue too large Convergence failure:
V(I6.N0.gi) = 0 V
residue too large: | -486.935 nA | > 43.0633 nA + 1 pA
The following set of suggestions might help you avoid convergence difficulties. After you have a solution, write it to a nodeset file by using the `write' parameter, and read it back in on subsequent simulations by using the `readns' parameter.
- Evaluate and resolve any notice, warning, or error messages.
- Perform sanity check on the parameter values by using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings. Print the minimum and maximum parameter value by using `info' analysis. Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.
- Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes.
- Enable diagnostic messages by setting option `diagnose=detailed'.
- Small floating resistors connected to high impedance nodes can cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.
- If you have an estimate of what the solution should be, use nodeset statements or a nodeset file, and set as many nodes as possible.
- Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.
- If simulating a bipolar analog circuit, ensure that the region parameter on all transistors and diodes is set correctly.
- Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence.
- If the analysis fails at an extreme temperature, but succeeds at room temperature, try adding a DC analysis that sweeps temperature. Start at room temperature, sweep to the extreme temperature, and write the final solution to a nodeset file.
- Increase the value of gmin (on options statement).
- Use numeric pivoting in the sparse matrix factorization by setting `pivotdc=yes' (on options statement). Sometimes, it is also necessary to increase the pivot threshold to a value in the range of 0.1 to 0.5 by using `pivrel' (on options statement).
- Try to simplify the nonlinear component models to avoid regions that might contribute to convergence problems in the model.
- Divide the circuit into smaller pieces and simulate them individually. However, ensure that the results are close to what they would be if you had simulated the whole circuit. Use the results to generate nodesets for the whole circuit.
- If all else fails, replace the DC analysis with a transient analysis and modify all the independent sources to start at zero and ramp to their DC values. Run transient analysis well beyond the time when all the sources have reached their final value (remember that transient analysis is very cheap when none of the signals in the circuit are changing) and write the final point to a nodeset file. To make transient analysis more efficient, set the integration method to backward Euler (`method=euler') and loosen the local truncation error criteria by increasing `lteratio', say to 50. Occasionally, this approach fails or is very slow because the circuit contains an oscillator. Often, for finding the dc solution, the oscillation can be eliminated for by setting the minimum capacitance from each node to ground (`cmin') to a large value.
Analysis `tran' was terminated prematurely due to an error.
finalTimeOP: writing operating point information to rawfile.
Error found by spectre during DC analysis, during info `finalTimeOP'.
ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point.
Analysis `finalTimeOP' was terminated prematurely due to an error.
******************
DC Analysis `dcOp'
******************
Error found by spectre during DC analysis `dcOp'.
ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point.
Analysis `dcOp' was terminated prematurely due to an error.
dcOpInfo: writing operating point information to rawfile.
Error found by spectre during DC analysis, during info `dcOpInfo'.
ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point.
Analysis `dcOpInfo' was terminated prematurely due to an error.
modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.
primitives: writing primitives to rawfile.
subckts: writing subcircuits to rawfile.
Aggregate audit (2:08:04 PM, Mon Nov 26, 2018):
Time used: CPU = 2.16 s, elapsed = 3.39 s, util. = 63.8%.
Time spent in licensing: elapsed = 69.4 ms.
Peak memory used = 69.5 Mbytes.
Simulation started at: 2:08:01 PM, Mon Nov 26, 2018, ended at: 2:08:04 PM, Mon Nov 26, 2018, with elapsed time (wall clock): 3.39 s.
spectre completes with 5 errors, 11 warnings, and 2 notices.