Access design variables from Verilog-A file

Hi,

I wonder if there are any way to access design variables in ADEXL from a Verilog-A file during a transient simulation?

I am sweeping a design variable in my ADE-XL session and running several simulations in parallel. During the simulation, i use a Verilog-A script to read simulation data and store to a .csv file. 

The problem is that when i run the simulations in parallel, i dont know in which order the simulations will be finished and hence the order of the results in the CSV file. If i could write the value of the design variable under sweep together with the simulated data, i could determine the order of the simulations in post processing of the CSV file. 

In below for MWE, i read the voltages vin and vinp at the first timestep after 1ns. 

module datacollect(inp,inn);
input inp,inn;
electrical inp,inn;
integer file;
integer found=0;
analog begin
@(initial_step) begin
file=$fopen("path/temp_data.csv","a");
found=0;
end
if($realtime>1e-9)
begin
if(found==0)
begin
$fwrite(file,V(inp),",","V(inn),",",sweep_var),",");
found=1;
end
end
end
endmodule

Thanks