Hi All
I am trying out to use amsd block to configure some cells to be bound to a spice netlist.
inside the amscf.scs file, I am writing some thing like:
include "analog_top.scs" //hierarchical netlist for whole analog design
include "modelfile.scs" section=tt //model files and section selection
include "analogControl.scs" //simulator and analysis settings
amsd{
portmap subckt=ana_top porttype=name autobus=yes
config cell=ana_top use=spice
ie vsup=1.5
}
My intentions is to use the schematic for whole analog top in the DUT.
Unfortunately, the end results is not good.
The ana_top cell has been resolved to "worklib.ana_top:spice-skeleton" as shown in the log file, with "-libverbose" option in irun.
But such "spice-skeleton" view contains no real content, just bunch of parameters.
And according to the simulation results/speed, it shows that the ana_top cell is indeed empty.
Does someone have clue about where may go wrong?
Best Regards
Yi
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