Hi All,
When generating the standard cell schematics (from .cdl) for an OA library from the scratch (in IC6), sometimes the discrepancies can be noticed between the symbol and schematic views, as in:
Warning: Terminal "RQ2B" in view schematic is (input) but is (output) in "REG2M1S symbol".
I use Import -> Spice.... to import the netlist of standard cells in .cdl format. The pin directions in the symbol seem to be correct. Is there a way to fix this issue at once for large number of cells?
Thanks in advance
Anuradha