Hello,
I am using ultrasim to simulate a spectre format netlist.
I want to stitch the capfile to the instance [XBLOCK.XRIBLET] using the following ultrasim option:
usim_opt capfile="[XBLOCK.XRIBLET] /gsa/pokgsa-p12/13/magnetarkj/FlowRethink/ExtractedBlocks/MG_CR_RIBLET.cap"
My capfile contains only many capacitances extracted from the layout:
Cg18300 (XWLBLK\<0\>.DRV8\<62\>.WLD\<4\>.net042 GND) capacitor c=5.28362e-15
Cg18299 (XWLBLK\<0\>.DRV8\<62\>.WLD\<0\>.ND20.net8 GND) capacitor c=1.43045e-17
Cg18298 (XWLBLK\<0\>.DRV8\<62\>.WLD\<0\>.ND0.net8 GND) capacitor c=1.82924e-17
Cg18297 (XWLBLK\<0\>.DRV8\<62\>.WLD\<0\>.ND20.net8@2 GND) capacitor c=1.39314e-17
Cg18296 (XWLBLK\<0\>.DRV8\<62\>.WLD\<0\>.ND0.net8@2 GND) capacitor c=1.76248e-17
Cg18295 (XWLBLK\<0\>.DRV8\<62\>.WLD\<0\>.net041 GND) capacitor c=2.07346e-15
Cg18294 (XWLBLK\<0\>.DRV8\<62\>.WLD\<0\>.net087 GND) capacitor c=2.4252e-15
Cg18293 (XWLBLK\<0\>.DRV8\<62\>.WLD\<0\>.WRSELXX GND) capacitor c=6.01831e-15
Cg18292 (XWLBLK\<0\>.DRV8\<62\>.WLD\<0\>.net029 GND) capacitor c=2.10627e-15
When I run ultrasim, The stitching does not occur
I obtain the following error types in the spfrpt:
18300 errors and 0 warnings(fixed errors) are issued (see file "stimulis.spfrpt")
***** File "/gsa/pokgsa-p12/13/magnetarkj/FlowRethink/ExtractedBlocks/MG_CR_RIBLET.cap" ****** :
ERROR (STITCH-0012)(:1) : Syntax error in Cg18300
ERROR (STITCH-0012)(:2) : Syntax error in Cg18299
ERROR (STITCH-0012)(:3) : Syntax error in Cg18298
ERROR (STITCH-0012)(:4) : Syntax error in Cg18297
ERROR (STITCH-0012)(:5) : Syntax error in Cg18296
ERROR (STITCH-0012)(:6) : Syntax error in Cg18295
ERROR (STITCH-0012)(:7) : Syntax error in Cg18294
....
The syntax of a capacitor in spectre format seems to me correct. Thus I do not understand the problem.
Please advise,
Regards,
Kotb