I have an on-going battle with Virtuoso trying to make things work and/or not look disgusting with everything on a white background (so I can always have WYSIWYG when I print stuff). I made my own display.drf file that contains (so far) only the things I need to make schematics look good on a white background. My most recent hurdle was figuring out what defined the color of selected items like wires or labels etc. Before I fixed it, that color was white (which annoyingly makes the selected items invisible on a white background). For the technology I'm using, the solution proved to be the following line in my display.drf file:
; color of selected items (lpp = align/drawing).
( display defaultPacket blank dashed red red outline )
However, I've since found as I bring more tools into the fold that I need to prevent my display.drf file from loading first because (for reasons unknown to me) it appears to block other display.drf files from other libraries loading. To get around that I added the following to my .cdsinit:
; Force Cadence to load the tsmc18 library and read it's display.drf file first
ddGetObj("tsmc18")~>techLibName
; Now superimpose my display.drf file on top of it
; The nil means it won't ask you to save it when you quit Virtuoso
drLoadDrf("./display.drf" nil)
After I do the above, everything in my schematics continues to look as per my display.drf *except* for the color of the selected items as outlined above - they're coming out as white again :-(.
I'm guessing maybe another rogue display.drf file is being loaded after mine, but darned if I know to determine or fix that. Any ideas?
Note that I realize I could just let everything load up, go into the Display Resource Editor and then merge my display.drf file into it and save the result (assuming "merge" means anything set in my file overrides existing stuff). However, that would become a maintenance nightmare after a while as I move from project to project.