Hi,
I have a .scs model file for a digital block. The digital block has some multi-bit (bus) outputs. At the end of the .scs file, there are a bunch of statements to drive the outputs of the blocks:
v1 (demux\<0\> gnd) vsource type=dc dc=0
and this is repeated for each bit of the multi-bit signal.
This model file is added: ADE -> setup -> simulation files --> (added in the definition files category), and the testbench runs successfully.
Instead of driving each bit along, I would like to drive the whole bus (ideally with an analog value that gets translated during simulation). I have a VerilogA analog to digital component (tested and works) that I would like to use to drive that bus, the syntax that I used is:
AD1 (demux\<3\:0\>) adc_4b one=vdd zero=0 num=demux_val
At first the simulation failed complaining that adc_4b is not defined (although the library containing it is added to the library path in the library manager). I added the veriloga (.va) file that defines the component, once to setup--> simulation files --> definition files, and once to setup--> model files, and in both times the simulation fails because of a whole bunch of errors that seem to be VerilogA parsing errors, for example:
ERROR : (SFE - 874) "path" : unexpected quote character "`". Cannot run the simulation because of syntax error.
and so on.
veriloga is added to the switch view and stop view fields in setup --> environment
I am using IC6.1.7-64b.500.16
Thank you in advance