Good afternoon!
I've been trying to run a simulation for analysing the hysteresis of a given comparator, but with no success. I'm following De la Rosa's "CMOS Sigma-Delta Converters" book, where he runs a test-bench for hysteresis analysis using the input-ramp method. Problem 1: I can't see the circuit properly because the pdf I have has an awful resolution, so I made my own circuit, adding what I could properly see on the book. I ran some parametrics using a delay variable in the latch vsource and though I got an output similar to the book, the Vhy value will vary according to how many steps I set in the parametrics analysis.
Fig1 - De la Rosa's circuit
Fig2 - My circuit
Fig3 - Book's output
Question 1: How can this method be reliable if Vh varies according to how many steps I set in the parametrics analysis?
Question 2: Is there any other way I could do hyst analysis?
Thank you for your attention!