Currently Simulating a boost converter with a comparator and Tapered Buffer, my Error Amp will be simulated after I will get a very good result with this one:
Specs:
Tech Node = 65nm
500mV = input
2.5V = Output
Duty Cyle = 80%
PMOS = w/l (4u/2u) m = 1.5k
NMOS = w/l (1.5u/1u) m = 1.5k
Sfw = 1 MHz
RLC values in the picture
Output Voltage in the simulation: 870m V
PWM waveform:
I calculated the RLC components and duty cycle based on my Input and output, but I could not get a result at least close to 2.5V, Is it because I have to add the Error Amp first to see a good result?
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Boost Converter Design Help
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