Hello everyone!
When I complete the layout of a cmos inverter and try to implement the post-simulation of it, there is a warning:
It reminds me that some instances (source and load) and nodes are dangling and removed during the simulation so that no waveform generates after the simulation, but the pre-simulation is normal.
This is my circuit:
I wonder what causes it and if there is a method to solve it.
Thanks in advance for any ideas on how to best overcome this problem!
Maioca