error in digital verilog code

Good afternoon everyone,

I have an error in verilog coding . the following blue line indicates an error.

This is my error:

ncelab: *W,CUVMPW (./arraym8.v,7|26): port sizes differ in port connection (16/8).
array4  z1(u[3:0],v[3:0],s0[15:0]);
array4  z2(u[7:4],v[3:0],s1[15:0]);
array4  z3(u[3:0],v[7:4],s2[15:0]);
array4  z4(u[7:4],v[7:4],s3[15:0]);

This is my whole program for array multiplier for 8-bit:

module array8(u,v,y);
input [7:0]u,v;
output [15:0]y;
wire [15:0]s0,s1,s2,s3,y;
wire [7:0]s4,t1;
wire [11:0]s5,s6,t2,t3,t4;
array4  z1(u[3:0],v[3:0],s0[15:0]);
array4  z2(u[7:4],v[3:0],s1[15:0]);
array4  z3(u[3:0],v[7:4],s2[15:0]);
array4  z4(u[7:4],v[7:4],s3[15:0]);
assign t1 = {4'b0,s0[7:4]};
assign s4 = s1[7:0]+t1;
assign t2 = {4'b0,s2[7:0]};
assign t3 = {s3[7:0],4'b0};
assign s5 = t2+t3;
assign t4 = {4'b0,s4[7:0]};
assign s6= t4+s5;
assign y[3:0]=s0[3:0];
assign y[15:4]=s6[11:0];
endmodule

module array4(a,b,c);
input [3:0]a,b;
output [7:0]c;
wire [3:0]q0,q1,q2,q3,q4,temp1;
wire [7:0]c;
wire [5:0]q5,q6,temp2,temp3,temp4;
array2  z5(a[1:0],b[1:0],q0[3:0]);
array2  z6(a[3:2],b[1:0],q1[3:0]);
array2  z7(a[1:0],b[3:2],q2[3:0]);
array2  z8(a[3:2],b[3:2],q3[3:0]);
assign temp1 = {2'b0,q0[3:2]};
assign q4 = q1[3:0]+temp1;
assign temp2 = {2'b0,q2[3:0]};
assign temp3 = {q3[3:0],2'b0};
assign q5 = temp2+temp3;
assign temp4 = {2'b0,q4[3:0]};
assign q6= temp4+q5;
assign c[1:0] = q0[1:0];
assign c[7:2] = q6[5:0];
endmodule

module array2(d,e,f);
input [1:0]d,e;
output [3:0]f;
wire [3:0]f,temp;
assign f[0] = d[0]&e[0];
assign temp0 = d[1]&e[0];
assign temp1 = d[0]&e[1];
assign temp2 = d[1]&e[1];
ha z10(temp[0],temp[1],f[1],temp[3]);
ha z11(temp[2],temp[3],f[2],f[3]);
endmodule

 module ha(g,h,i,j);
input g,h;
output i,j;
assign i = g^h;
assign j = g&h;
endmodule

please help me to find my error/