Cellview generation from VHDL code in cadence 618

HI,

A beginer here for cadence,

I copy paste a wkng VHDL code from Vivado to cadence VHDL editor (Libray manager->file->new cellview : ... type :VHDL, open with : editor), save -> build a database of instancews,pins...   then following error is :

*WARNING* (TE-1308): Failed to perform syntax check for cellview 'CIS_v0 cnt_CTIA functional'.
*WARNING* (TE-1312): Compilation errors or warnings have been detected in the HDL file for cellview 'CIS_v0 cnt_CTIA functional'. To view the parse log for details, choose 'Parser Log File' from the 'View' menu.
*WARNING* (TE-4309): Extract failed for cellview 'CIS_v0 cnt_CTIA functional'

looking for any lead to resolve asap

thanks and regards,

rahul