Hi all,
Is there any way to know the maximum allowed Vds and Vgd voltage? I am using a 130 nm Bulk process with a supply voltage of 1.2 V. I am designing a class E and the drain voltage is equal to 3.5 * Vdd. Even with a cascode configuration, I get around 2.3V on the common source transistor. The cadence does not display any warning but It did not display a warning when the drain-source voltage was 3.8 so .
Do UMC or TMC usually release maximum ratings pdf's?
Cheers and thanks in advance
Alex