Hello,
After performing the layout exctraction step, the parasatice elements I can see it on the cell of the extracted view,
These elements are distributed everywhere and it is difficult to debug the circuit with regard these parasitics.
I am wondering if there is a tool that back annotates parasitic elements to the origional circuit schematic?
I am using Cadence Virtuoso version IC6.18-64b-500 and Assura tools
Thank you in advance
Best Regards