ignore instance by layout extraction

Hello,

I use the  iprobe that break the feedback loop of the amplifier in my design to perform the stability analyses,

Now I am doing the layout, but don't know how to make the iprobe ignored by the layout so I can pass the LVS, then later I will be able to use this probe for my post-layout simulation.

I use the Cadence Virtuoso version IC6.18-64b.500.6 with Assura package

Thank you in advance

Best Regards