Verilog Error

I was trying to compile the below code and ran into this error

module and_gate ( output reg Y,input A, B);
always @ (A or B) begin
    if(A==1'B1 & B==1'B1) begin
        Y=1'B1;
    end
    else
        Y=1'B0;
end
endmodule

Error: VAMS *E, NCVNF: Cannot find xmvlog executable in your path. Please update your path to point to the correct executable or use vmsNcvlogExecutable variable to specify the executable to use"